Fig. 10. Silicon photonics chip design.

Layout (left) of the full silicon photonics chip provided for fabrication at IMEC. Regions highlighted in green indicate the portions of the chip allocated to the testing of new geometries, functionalities, etc., at the individual device level. The red, yellow, blue, and black regions indicate the positions of four representative large-scale circuits utilizing a large number of individual devices. A microscope image (right) of the chip after fabrication and after custom MEMS postprocessing captures the full layout and scale. The aluminium rings are visible as bright contours, as is the exposed device layer silicon seen in pink inside the MEMS cavities. Note that the dark spots in the image are regions where the integrity of the alumina passivation was locally compromised and the vapour HF etchant could penetrate into the BEOL stack