Table 1.

Summary of synthesis results of the VLSI core.

Constrained Clock Period/Frequency	Critical Path Delay + Setup Time [ps]	Interconnect Area [µm2]	Combinational Area [µm2]	Flop Area [µm2]	Total Area [µm2]	Equivalent Gates Count	Static Power [µW]	Dynamic Power at Constrained Clock Frequency [mW]
50 ns/20 MHz	209	238.31	358.52	311.82	935.44	46,406.71	25.8	0.0 at 20 MHz
10 ns/100 MHz	209	238.31	358.52	311.82	935.44	46,406.71	25.8	0.1 at 100 MHz
1 ns/1 GHz	213	242.55	361.51	311.82	940.60	46,662.89	26.2	1.4 at 1 GHz
300 ps/3.33 GHz	203	246.70	364.02	312.02	947.76	47,017.95	26.5	4.8 at 3.33 GHz
250 ps/4 GHz	207	246.65	363.58	312.02	947.26	46,993.09	26.5	5.7 at 4 GHz
200 ps/5 GHz	196	262.31	370.36	311.82	974.62	48,350.56	27.0	7.3 at 5 GHz
175 ps/5.71 GHz	175	279.77	380.24	311.82	1006.29	49,921.55	28.1	8.9 at 5.71 GHz
150 ps/6.67 GHz	150	308.64	405.16	312.02	1070.99	53,131.20	30.8	11.4 at 6.67 GHz
130 ps/7.69 GHz	130	346.53	461.34	312.02	1192.14	59,141.85	36.7	15.2 at 7.69 GHz