Figure 3.
(a) Bright-field TEM micrograph of a sectioned nanowire device. The device structure consists of a buried SiO2 layer underneath the silicon nanowire. On top of the nanowire channel is the hBN dielectric, which is shown to cover the nanowire. A stack of Ti and Al serves as the gate electrodes above the hBN. (b) Corresponding superimposed EDXS-based element distribution maps of the hBN-silicon-nanowire-based device.