| EDaC | Error Detection and Correction |
| DVS | Dynamic Voltage Scaling |
| MEP | Minimum Energy Point |
| NTC | Near-Threshold Computing |
| DW | Detection Window |
| EP | Error Prediction |
| PW | Prediction Window |
| EDC | Error Detection Circuit |
| EPC | Error Prediction Circuit |
| ECC | Error Correction Circuit |
| ARs | Architecture Registers |
| SoTA | State-of-The-Art |
| DS | Double Sampling |
| TD | Transition Detection |
| IO | Input–Output |
| PoFF | Point of First Failure |
| DPAD–EDaC | Deep Path Activity Detection–EDaC |
| SEL | Shared Error Latch |
| DEP | Distributed Error Processor |
| RTL | Register Transfer Level |
| MC | Monte Carlo |
| STA | Static Timing Analysis |