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. 2023 Sep 19;106(3):00368504231201792. doi: 10.1177/00368504231201792

Table 3.

Semiconductor stresses in the proposed circuit.

Voltage stress Current stress
Smain Vi IL
S1, D1 Vo1 Io
S2, D2 Vo2 Io
S3, D3 Vo3 Io