Fig. 4. Monolayer MoS₂ memtransistor-based “hunger neuron” and “appetite neuron”.

a Optical image and b circuit schematic of a representative comparator circuit composed of 8 MoS₂ memtransistors (${\mathrm{MT}}_1$–${\mathrm{MT}}_8$) used as the “hunger neuron” and the “appetite neuron”. The comparator circuit is a 4-stage cascaded inverter as each memtransistor pair, ${\mathrm{MT}}_1-{\mathrm{MT}}_2$, ${\mathrm{MT}}_3-{\mathrm{MT}}_4$, ${\mathrm{MT}}_5-{\mathrm{MT}}_6$, and ${\mathrm{MT}}_7-{\mathrm{MT}}_8$ serve as an inverter. c ${\mathrm{V}}_{\mathrm{N}4}$ measured at node, $\mathrm{N}4$. d $V_{\mathrm{N}5}$ measured at node, $\mathrm{N}5$. e $V_{\mathrm{N}6}$ measured at node, $\mathrm{N}6$, and f $V_{\mathrm{N}7}$ measured at node, $\mathrm{N}7$, as a function of the input voltage, $V_{\mathrm{N}2}$, applied to node $\mathrm{N}2$. Peak gain for each inverter stage is mentioned in the inset. Highest gain of ~90 is observed for the output stage, which allows for the abrupt state transition for $V_{\mathrm{N}7}$ from 0 to $V_{\mathrm{DD}}$, i.e., logic “0” to logic “1”. The input voltage, $V_{\mathrm{N}2}$, at which this sharp state transition occurs is referred to as the comparator threshold ($V_{\mathrm{TH}-\mathrm{C}}$). For the “hunger neuron” and the “appetite neuron”, $V_{\mathrm{TH}-\mathrm{C}}$ is represented by $V_{\mathrm{HN}}$ and $V_{\mathrm{AN}}$, respectively, and $V_{\mathrm{N}7}$ is represented by logic state variables $\mathrm{H}$ and $\mathrm{A}$, respectively. Temporal evolution of $V_{\mathrm{H}}$, i.e., logic state of $\mathrm{H}$ in response to g sweet and h bitter taste stimulants. Temporal evolution of $V_{\mathrm{A}}$, i.e., logic state of $\mathrm{A}$ in response to i sweet and j bitter taste stimulants. k Transfer curve for the “appetite neuron” for different $V_{\mathrm{AN}}$ obtained through non-volatile programming of MoS₂ memtransistor, ${\mathrm{MT}}_2$. Corresponding temporal evolution of $V_{\mathrm{A}}$ or $\mathrm{A}$ in response to l sweet and m bitter taste stimulants.