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. Author manuscript; available in PMC: 2023 Oct 20.
Published in final edited form as: Proc IEEE Inst Electr Electron Eng. 2022 Oct 17;110(10):1538–1571.

TABLE IV.

The heteroassociative item memory implementing rule 110.

Address (input) Content (output)
h111 = [l1 + c1 + r1] 0
h110 = [l1 + c1 + r0] 1
h101 = [l1 + c0 + r1] 1
h100 = [l1 + c0 + r0] 0
h011 = [l0 + c1 + r1] 1
h010 = [l0 + c1 + r0] 1
h001 = [l0 + c0 + r1] 1
h000 = [l0 + c0 + r0] 0