Table 9.

Comparison of hardware PQC accelerations.

Design	TCHE’20 [13]	IEEE Access’21 [14]	FPL’20 [32]	TCHE’19 [11]	TCAS-I’20 [16]	This Work
Platform	ASIC (65nm)	FPGA (ZCU106)	FPGA (VIRTEX-7)	ASIC (40nm)	ASIC (28nm)	ASIC (28nm)
Frequency (MHz)	45	100	-	72	300	150
Gate Counts (kGE)	${57}^a$	-	-	106 e	37 + ${942}^f$	477 + ${54}^g$
Complexity (LUT/FF/DSP/BRAM)	-	178/0/5/$0.5^b$ 377/0/10/$0.5^c$	417/462/0/$0^d$	-	-	-
Accelerator Type	Tightly Coupled	Tightly Coupled	Tightly Coupled	Memory-mapped	Coprocessor	Coprocessor
Supported NIST PQC algorithms	Kyber Saber	Kyber Dilithium	Kyber Dilithium Falcon	Kyber Dilithium	Kyber	Kyber Dilithium Falcon SPHINCS+ BIKE HQC Classic McEliece

^a Includes Pulpino w/o FPU. ^b Only for additional ALU logic for Kyber. ^c Only for additional ALU logic for Dilithium. ^d Only for additional accelerator. ^e Includes baseline CPU core. ^f SCR1 core and the vector coprocessor, respectively. ^g CVA6 core and the coprocessor, respectively