Table 1.

Comparison of CX depth ($d_{\mathit{CX}}$) for parallel versus serial implementations of the UCR gate on $n_a=n_d\in \{4,5,6,8,10\}$ qubits.

$n_a$	(# address qubits)	4	5	6	8	10
$n_d$	(# data qubits)	4	5	6	8	10
$d_{\mathit{CX}}$	Parallel UCR	16	32	64	256	1025
	Serial UCR	32	81	193	1025	5121
	Reduction	$2.1\times$	$2.5\times$	$3.0\times$	$4.0\times$	$5.0\times$