Table 1.
Key structure and process parameters for various structure transistors.
| Transistor structures | Planar | CFET or | Vertical | |||
|---|---|---|---|---|---|---|
| and technology | transistor | FinFET | GAAFET | 3DS FET | transistor | |
| 1 | Process node | ∼22 nm\20 nm | 22–3 nm | 3–1 nm | ∼1 nm | Beyond |
| 2 | CGP | >80 nm | 80–48 nm | 48–38 nm | 40–36 nm | 80–48 nm |
| 3 | Gate length | >24 nm | 24–14 nm | 14–10 nm | 12–10 nm | >20 nm |
| 4 | EOT | >0.9 nm | ∼1.0 nm | ∼1.0 nm | <1.0 nm | ∼1.0 nm |
| 5 | SDC tracks | >7.5 T | 7.5–6 T | 6–5 T | <5 T | <5 T |
| 6 | Transistor density | <0.5 B cm−2 | 0.5–30 B cm−2 | 30–300 B cm−2 | >300 B cm−2 | >300 B cm−2 |
| 7 | Power voltage | <0.9 V | 0.9–0.7 V | 0.7–0.6 V | 0.7–0.6 V | 0.9–0.6 V |
| 8 | Performance factor per footprint | 1 | 2–2.5 | 3–6 | 6–12 | 5–10 |
| 9 | Scaling factor | >10 nm | ∼4 nm | ∼3 nm | ∼3 nm | ∼3 nm |
| 10 | Gate control per channel | 1 | 2–3 | 4 or all round | 4 or all round | 4 or all round |
| 11 | Fine lithography per footprint | i-193 nm ArF | MP, EUV | MP, HNA EUV | MP, HNA EUV | i-193 nm ArF, MP |
| 12 | Key process | Strain, HKMG | Strain, HKMG, | Strain, HKMG, | HKMG, | HKMG, |
| technology | DTCO | DTCO, BSPDN | STCO, BSPDN | DTCO | ||
| 13 | Channel doping | SSRW, peak | Uniform | Uniform | Uniform | Uniform |
| 5 × 1018 cm−3 | 3 × 1016 cm−3 | 1 × 1016 cm−3 | 1 × 1016 cm−3 | 1 × 1016 cm−3 | ||
| 14 | Channel material | Si | Si, SiGe | Si, SiGe | Si, SiGe, Ge, | Si, SiGe, |
| CNT, 2DM, AOS | III-V | |||||
| 15 | Channel carriers | DD | Q-Ballistic | Ballistic | Ballistic | Ballistic |
| conductance | tunneling, NC | tunneling, NC | ||||