Novel level and edge-triggered universal shift registers with low latency in QCA technology

Abstract

Shift registers are one of the main blocks in processors. In this paper, two new universal shift registers are designed based on Quantum-Dot Cellular Automata (QCA) nanotechnology. Both of the proposed level triggered and edge triggered universal shift register in QCA technology shows good performance in regards of the number of cells, occupied area, delay, and power. These designs also have reset abilities. Simulations show that the proposed 4-bit level triggered universal shift register with reset ability has 1057 QCA cells, 1.27 μm² occupied area, and delay of about three cycles of QCA clock. In addition, the proposed rising edge triggered 4-bit universal shift register with reset ability has 1085 QCA cells, 1.27 μm² occupied area, and delay of about three cycles of QCA clocks.

1. Introduction

The electronics industry is developing from the initial invention of the vacuum bulb up to CMOS at present. Today, CMOS technology is known as the most widely used technology in the field of electronics [[1], [2], [3], [4], [5]]. Considering the applications and benefits of CMOS technology, improvements such as increasing the operation frequency and reducing power consumption are required [[6], [7], [8], [9]]. QCA technology is one of the proposed technologies for replacing CMOS technology in digital electronics [[10], [11], [12], [13]]. QCA technology has advantages such as higher operation frequency, smaller dimensions, and lower power consumption than CMOS technology. It is hoped that the QCA technology will revolutionize the digital industry.

Registers and shift-registers are the most widely used circuits in digital electronics. Shift-registers are commonly used in the output and input ports, memory circuits and counter construction. Various types of shift-registers are available, such as series shift-registers and parallel shift-registers. The most comprehensive type of shift-registers is the so-called “Universal” shift-register, which has the whole capabilities of the other shift-registers. There are different designs with respect to the vast application of universal shift-registers. In Ref. [14], a design is presented for an 8-bit universal shift-register. In this scheme, a design has been introduced for a D-latch in QCA technology using logic gates. In Ref. [14] the proposed D-latch has no reset function and an AND gate is used in the output to establish “enable” functionality. In addition, some models of 4:1 and 8:1 multiplexer are presented. The Signal Distribution Network (SDN) method [[15], [16], [17]] has been used to pass the wires and connect the pins. The use of this method has led to a sharp increase in the latency, size, and number of circuit cells. Furthermore, in Ref. [18], designs of 4-bit and 8-bit universal shift-registers were also presented. In the proposed designs, the laying method was used for passing wires [19]. The use of multi-layers leads to design complexity and disassembled inputs and outputs. On the other hand, level sensitive flip-flops have been used in the past. For more diverse applications, there is a need for a smaller edge sensitive design with lower cell numbers and delay. In Ref. [20] a new design of shift register is announced, but the proposed design is not a universal shift register. In addition, a new shift register, and universal shift register are proposed in Ref. [21]. These designs in Ref. [21] have no reset terminals which is an inevitable option in digital circuits. Also, in these designs' inputs are placed inside the circuit and this led to routing problems. Therefore, in this paper, a novel universal shift register will be proposed which has a fewer number of quantum cells and delay and occupies the smaller area. Also, the proposed design has a reset terminal. The proposed universal shift register can be used in more complex circuits since all inputs and outputs are available.

The paper is organized as follows. QCA principles are described in the following. The universal shift-register function is examined, and previous designs are studied. Universal shift-register designs are introduced, and simulation and power analysis results are presented. Finally, proposed schemes are compared with existing ones.

2. Principles of QCA

QCA technology. Fig. 1 (a) shows a QCA cell. A QCA cell contains four quantum cavities in which two extra electrons are charged [22]. The electrons can move through the tunneling mechanism between quantum dots, but they cannot transmit to another cell. The coulomb's repulsion force makes the electrons place in cavities in two stable locations. Electron positions are introduced with poles of +1 and −1. The polarities of +1 and −1 denote binary 1 and binary 0 respectively. Fig. 1 (b) shows how electrons are located within the cells of 90° and 45°.

Fig. 1.

(A) QCA cell, (b) how electrons are placed in cells (45° and 90° cells).

By putting a chain of cells together, a single-wire model can be implemented. The coulomb's repulsion force makes it possible to transmit binary information between cells. Fig. 2 (a) shows two wires models with 90° and 45° cells [23,24]. There are several ways to pass the wires from one node. The first method is to use 90° and 45° cells according to Fig. 2 (b) [20]. This method may damage information in complex circuits. Crossing over can also be used to pass the wire. To use this method, at least three layers are needed (Fig. 2 (c)). Another kind of wire crossing is also defined in Ref. [25].

Fig. 2.

(A) 45° and 90° wires, (b) One layer Cross over using 90° cells, (c) Multilayer Cross over.

We can implement logic gates in QCA technology based on electromagnetic interactions. For example, by making a simple change in a binary wire, a logic gate is constructed according to Fig. 3 (a). Three-input majority gate is the base gate in QCA technology. By modifying the three-input majority gate in accordance with (1), we can create the same function as “AND” and “OR” gates. Fig. 3 (b) illustrates how to organize the three-input majority gate in QCA technology [26,27] is shown by (1):

$$\begin{array}{l}MAJ\left(A.B.C\right)=AB+AC+BC\\ \begin{array}{c}MAJ\left(A.B.0\right)=AB\\ MAJ\left(A.B.1\right)=A+B\end{array}\end{array}$$ (1)

Fig. 3.

(A) NOT gate in QCA, (b) Majority gate in QCA.

Timing in QCA is controlled by clock [28]. The clock in the QCA is performed in four stages and four separate phases with a difference of 90°, thus data flow is controlled in the circuit. Each phase is called the clock zone, which consists of four steps called switch, hold, release and relax [29,30]. Fig. 4 (a) shows the clock curves phases and cell colors according to their clock regions. All four clock zones are considered as a delay cycle in the QCA. By utilizing cells with 180 degrees of the phase difference, we can pass the wires from one node [31,32]. Fig. 4 (b) shows how the wires are passed based on the clock phase difference.

Fig. 4(A).

clock zones, (b) Wire crossing using clock.

3. Proposed shift register design

Shift registers are electronic devices that are widely used in various applications for data storage and manipulation. They are particularly useful for serial-to-parallel or parallel-to-serial data conversion, data delay, and data synchronization. One common application of shift registers is in digital communication systems. They are used to convert parallel data into a serial stream for transmission over a single communication channel. This allows for efficient data transfer and reduces the number of required transmission lines. Shift registers are also used in serial data reception, where they convert the received serial data into parallel form for further processing. This is commonly seen in applications such as serial communication interfaces (e.g., UART) and data acquisition systems. Another important application of shift registers is in digital counters and frequency dividers. By connecting the output of a shift register to its input, a feedback loop is created, allowing the register to cycle through a sequence of states. This enables the generation of various timing signals, such as clock signals or frequency division. In addition, shift registers find applications in data storage and memory systems. They can be used to store and retrieve data in a sequential manner, making them suitable for applications like shift register memory or shift register file storage. Overall, shift registers play a crucial role in digital systems, providing efficient data manipulation, storage, and synchronization capabilities in a wide range of applications. A shift register is made up of a few Flip-Flops, and each Flip-Flop can store one bit of information. An n-bit register is composed of n sets of flip-flops [33]. The simplest 4-bit register is a set of 4 D-flip-flops that have the same pulse-clock input and reset line. In this case, when each clock pulse is activated, the information existing on the inputs will be stored in the flip-flops and transmitted to the outputs. When the reset pin is activated, all stored data are cleared, and the outputs are changed to zero. This type of register is referred to as a register with parallel loading. A register that can transfer binary information to the left and right is called the shift-register. A shift-register consists of a set of flip-flops that are connected in a chain and have a common clock pulse. In this case, with each clock pulse, the information of a unit is moved to the left or right. If the input of the flip-flops chain is on the left, the shift-register does the shift to the right function. In the case where the flip-flops output is available, the information can be entered in series and received in parallel from outputs.

The most comprehensive type of shift-register is called universal shift-register. A universal shift-register can load parallel shift to the left and shift to the right. In the universal shift register, in addition to the D flip-flop, there are a number of 4:1 multiplexer. Fig. 5 shows the block diagram of the 4-bit universal shift-register. The bases S0, S1 are responsible for controlling the shift-register mode. In case of S0 = 1 and S1 = 1, the shift-register is in parallel loading mode, and with each clock pulse, the data available on the IN (3, 2, 1, 0) pins are written to the outputs in parallel.

Fig. 5.

4-bit Universal shift register.

In the case of S0 = 0 and S1 = 1, the shift-register is in the shift to left mode, and SHIFT L pin acts as an input. With the first clock pulse, a bit of data is stored in D flip-flop and appears in OUT0. With the next clock pulse, the value available in the D0 flip-flop is transmitted to D1 flip-flop and the new input is stored in D0 flip-flop, and this continues up to D3 flip-flop.

In the case of S0 = 1 and S1 = 0, the shift-register is in the shift to right mode, and SHIFT R base is considered as shift the input to the right. With the first clock pulse, a bit of data is stored in D3 flip-flop from SHIFT R pin. With the next clock pulse, the value available on the D3 flip-flop is transmitted to D2 flip-flop and the value available on SHIFT R is replaced in D3 flip-flop, and this continues up to D0 flip-flop. .

Table-1.

Modes of operations of Universal shift register.

Bus (S1,S0)	S1	S0	Operation
0	0	0	Unchanged
1	0	1	Shift right
2	1	0	Shift left
3	1	1	Parallel load

In the case of S0 = 0 and S1 = 0, the inputs are off the circuit and the data available on the flip-flops do not change. Table 1 shows how shift-register modes. The CLK pin is the clock input and RST pin acts as a reset line, and each time the RST pin is activated, all of outputs change at once to binary zero.

In order to implement the shift register according to the block diagram of Fig. 5 in QCA technology, the main blocks of shift registers must be designed first, and then, the blocks using different methods will be connected with each other. In the design presented in Ref. [14], the SDN method is used to pass the wire. In this method, a delay cycle is required to pass both wires from one node. Using SDN method in the 4 to 1 multiplexer increases 3.75 cycles to circuit delay. On the other hand, the presence of multiple wires in the flip-flop blocks cause a drastic increase in the final design latency. In the final design developed in Ref. [14], the delay for 8-bit universal shift-register has reached 8.75 cycles. The presence of this delay in the circuit is very unfavorable. In Ref. [34], the 90- and 45-degree cells are used for wire routing. The delay of 4:1 multiplexer improved equally to a cycle compared to the proposed scheme in Ref. [14]. The final design presented is a 2-bit universal shift-register with a delay of 6.25 cycles. In the proposed scheme of [18], the final delay has been reached to 4 cycles by deploying a laying method to pass wires [18]. However, the use of multi-layers can lead to design complexity. On the other hand, in all the above designs, the number of cells and circuit dimensions are not optimal.

Logical gates are used in all mentioned multiplexers designs. In Ref. [35], a new design is proposed for a 2to1 multiplexer. The delay in this design is 0.25 cycles. Subsequently, we have implemented a 4:1 multiplexer using this 2to1 multiplexer. The proposed multiplexer design is a single-layer and has a 1-cycle delay and 61 cells. Using this multiplexer would reduce the final universal shift-register circuit delay. It should be noted that as can be seen in the comparison table in Ref. [35], this multiplexer has better performance than other designs in terms of area, delay and number of used cells and easily can be used in more complex designs. In all the previous universal shift-registers design, a D latch has been used instead of a D flip-flop. The multiplexer provided in Ref. [35] can also be used to design a D latch [36]. By using feedback of the output to zero input of the multiplexer, the circuit acts as a D latch. By placing an “AND” gate in the feedback path, the reset function would be added to the circuit. Fig. 6 shows a D latch block diagram using a multiplexer. The reset function in this circuit acts as active low. Table 2 shows how the D latch with reset function can work.

Fig. 6.

Block diagram of D-latch.

Table-2.

D-Latch operation.

RST	CLK	D	OUT
1	0	0	OUT (t-1)
1	0	1	OUT (t-1)
1	1	0	0
1	1	1	1
0	X	X	0

The proposed new universal shift-register circuit is presented in Fig. 7. The proposed new universal shift register as can be seen has better performance than previous designs in many aspects such as: delay, area, and number of used cells. This design also has reset terminal which cannot be seen in previous works. The specified latches and multiplexer blocks have been used in the proposed architecture. In the proposed design, cells with 180 degrees of phase difference have been used to pass wires. In this design, the clock zone was executed in a way that cells with a 180-degree phase difference are reached together at the place where the wires intersect each other. In this situation, the wires can easily be passed from a point with no need for layering or other introduced methods. Thus, in the final design, the delay is 3 cycles, the number of cells is 1220, and circuit has 1.57 μm² dimensions. Despite the circuit is single-layer, significant improvements have been obtained compared with previous circuit designs.

Fig. 7.

Proposed 4-bit Universal shift register implemented in QCA using D-latches with reset ability.

Utilizing the multiplexer provided in Ref. [35] has resulted in significant improvements in the universal shift-register designs in comparison with existing ones. Optimizing 4:1 multiplexer can further improve the final design. Fig. 8 illustrates the universal shift-register circuit using improved multiplexers. The changes and improvements of multiplexers can be seen in terms of size and number of cells in Fig. 8. After applying these changes, the number of cells decreased to 1057, and the dimension of the design is reduced to 1.27 μm², which can be seen in this figure.

Fig. 8.

Optimized version of proposed level-triggered 4-bit universal shift register implemented in QCA.

As mentioned, D latch is used in the past designs and in the design of two proposed circuits. Latches work as a level sensitive flip-flops. In many cases, such as the construction of counters, employing clock edge sensitive circuits is essential. For example, flip flops in Refs. [37,38] can be used to implement shift registers. In Refs. [39,40], an edge sensitive converter design is provided. After adding the presented converter to the CLK input at D latch, D flip-flop is obtained as is shown in Fig. 9. Table 3 shows the rising edge sensitive D flip-flop performance.

Fig. 9.

Block diagram of D-Flip flop.

Table-3.

D-FF operation.

RST	CLK (t-1)	CLK(t)	OUT
1	0	0	OUT (T-1)
1	0	1	D
1	1	0	OUT (T-1)
1	1	1	OUT (T-1)
0	X	X	0

There are several ways to use the level to edge converter in the proposed universal shift-register. The first way is to place a level to edge converter for each D latch individually. In this case, the number of design cells will increase. Another method is to use a converter before the CLK input in the shift-register. In this method, the input clock first turns from level to edge, and then it enters the shift register. By this the final circuit delay of level to edge converter is increased. We can prevent increased delay by implementing the converter in the path between original CLK and D latches CLK input. Fig. 10 shows the proposed rising edge sensitive 4-bit universal shift-register. In this design, two converters have been used to convert latches to flip-flops. The sections that are separated by blue are the level to edge converters. Implementing converters in the path between CLK and latches has prevented the circuit delay. As a result, the final delay has been remained constant in 3 cycles, dimensions are 1.27 μm², and number of cells reached 1087 as well. Despite the added rising edge function, the design continues to be remarkably superior in terms of dimensions, cells numbers and delays compared with previous designs.

Fig. 10.

Proposed rising edge triggered Universal shift register implemented in QCA.

4. Simulation and results

The QCADesigner software has been used to simulate proposed designs. QCADesigner has two powerful processing engines, CoherenceVector, and Bistable Approximation, which can simulate QCA complex circuits with high precision [41,42]. The parameters applied simulations are presented in Table 4 [43].

Table 4.

Parameters model in the QCADesigner simulator.

Parameter	Value
Cell size	18 nm*18 nm
Dot diameter	5 nm
Cell separation	2 nm
Simulation engine	Bistable approximation/coherence vector
Radius of effect	65 nm
Number of samples	12,800
Convergence tolerance	0.0010000
Temperature	1.000000
Relative permittivity	12.900000
Clock high	9.800000e-022
Clock low	3.800000e+023
Clock shift	0.000000e+000
Clock amplitude Factor	2.000000
Layer separation	11.500000
Maximum iterations per sample	100

Fig. 11 shows the proposed design simulation results. In this simulation S0 = 1, S1 = 0 and the shift-register is in the shift to right mode, and CLK input is 1. The input data is applied to the SHIFT R pin. After 3 cycles of delay, the first data on the first flip-flop is stored from the left (D3) and appears in OUT3. After 3 cycles, the value available in OUT3 is stored in the flip-flop (D2) and appears in OUT2. The data is then transferred to the next flip-flop at the right with 3 cycles delay. The shift to left function of shift-register presented in Fig. 8 is shown in Fig. 12. In this case, S0 = 0, S1 = 1, and the data are entered into the SHIFT L input. After 3 cycles, the first data is stored in the D0 flip-flop. After the second 3 cycles, the value in D0 is shifted to the left and stored in D1, and the new input is replaced in D0, and the same operation continues. Fig. 7 has the same function as Fig. 8 and is ignored to avoid repeating. It should be mentioned that in the whole of these simulations. CLK is in the active case.

Fig. 11.

The simulation of Proposed design of Fig. 8, in shift to right mode.

Fig. 12.

The simulation of Proposed design in Fig. 8, in shift to left mode.

Fig. 13, Fig. 14 show the simulation results of the rising edge sensitive universal shift-register shown in Fig. 10 in the shift to right and shift to left modes, respectively. With each rising edge in CLK a data enters to the circuit. The delay of regions specified by red is due to the circuit delay itself (3 cycles), and regions separated by red are the delays due to the waiting to reach rising edge. In Fig. 15, the rising edge sensitive shift-register presented in Fig. 10 is in parallel loading position (S0 = 1, S1 = 1). IN0,1,2,3 inputs are converted to a BUS, and when each rising edge reaches, a data is stored in the flip-flops after 3 cycles of delay. Red arrows show reset activation. Because reset is Active Low, in areas where reset value is 0, outputs are zero.

Fig. 13.

The simulation of Proposed design in Fig. 10, in shift to right mode.

Fig. 14.

The simulation of Proposed design in Fig. 10, in shift to left mode.

Fig. 15.

The simulation of Proposed design in Fig. 10, in parallel mode.

Another use of universal shift-register is performing multiplication by 2 and division by 2. Each time, shifting a binary number to the right equals to dividing by 2. Also, each time shifting a number to the left is equal to multiplication by 2. This operation is shown in Fig. 16, using the proposed shift-register presented in Fig. 8. The inputs and outputs are becoming BUS. First, the circuit is in parallel loading mode and the binary equivalent of 14 is applied from the input BUS. After 3 cycles, the number 14 delay appears in BUS (OUT). In the next step, the stored number is shifted to the right in two times, and with each shift the number is divided by 2 one time. Finally, the circuit is in shift to left mode, and the shift to left is done two times, and with each shift the value is multiplied by 2.

Fig. 16.

The simulation of Proposed design in Fig. 8 used to divided by 2 and multiplied by 2.

The QCAPro tool is used to analyze the power of QCA circuits [44,45]. The proposed structure has been evaluated at three different levels of tunneling energy (0.5 EK, 1.0 EK, 1.5 EK) at 2.0 K. The results obtained are presented in Table 5. Fig. 17 shows the loss map in the case of 0.5 EK for the proposed scheme in Fig. 10. Cells with high loss are marked with dark color.

Table-5.

Analysis of energy consumption of proposed designs.

	Average Leakage Energy Dissipation			Switching Energy Dissipation Average
	0.50 EK	1.00 EK	1.50 EK	0.50 EK	1.00 EK	1.50 EK
Fig. 7	0.38177	1.16197	2.07675	0.02694	0.02328	0.01973
Fig. 8	0.33744	1.01683	1.80947	0.10006	0.08517	0.07144
Fig. 10	0.34684	1.04298	1.85520	0.84130	0.72583	0.61486

Fig. 17.

Power dissipation map for the proposed design in Fig. 10 with 0.5 Ek.

5. Conclusion

In this paper two new efficient designs for universal shift registers in QCA technology are reported. Shift registers are the main building blocks in processors and memory designs. The first proposed universal shift register is constructed from D latches and the second novel design is based on D flip flops. Both designs have reset pin to add the ability of reset for universal shift register. Despite using D flip flops and adding reset pin, the design continues to be remarkably superior in terms of dimensions, cells numbers and delays compared with previous designs which just use D latches without reset ability.

The proposed designs are compared with existing ones. The results prove that the proposed designs have remarkable advantages over previous designs. For example, the design proposed in Fig. 11, despite the addition of edge sensitivity, has improved 25% compared with the best existing design in terms of dimensions. Also, the proposed design in Fig. 8 has improved 20% in terms of cells numbers compared to the best available design. The improvements are illustrated in Table 6 and Fig. 18 diagrams. Fig. 18 shows the comparison diagrams of proposed designs in regards of number of cells, area and delay. A comparison with previous designs is abbreviated in Table-6. As can be seen none of the previous works has reset terminal. Also, all the previous designs are level sensitive while the current work has both level sensitive and edge sensitive designs with reset terminal. It should be noted that converting level to edge sensitive universal shift register and adding reset terminal led to use more cells, occupying more area and delay. We try to have all the following advantages while keeping the number of cells, area and delay in a reasonable range. The other advantages of the proposed designs is that all of the inputs and outputs are placed out of the designs which led to easier routing (this cannot be seen in previous works).

Table 6.

Comparison of the proposed QCA shift register with existing circuits for different number of bits.

References	bits	Cell Count	Area (nm2)	Cell/bits	Area/bits	Latency	Sensitivity	Reset
[14]	8	4035	6.33	504.37	0.791	8.75	Level	No
[18]	8	2937	3.52	367	0.44	4	Level	No
[18]	4	1343	1.67	335.75	0.4175	4	Level	No
[32]	2	769	1.45	384	0.75	6.25	Level	No
[21]	4	1048	1.04	262	0.26	3.25	Level	No
Fig. 7	4	1220	1.57	305	0.39	3	Level	Yes
Fig. 8	4	1057	1.27	264.25	0.31	3	Level	Yes
Fig. 10	4	1085	1.27	271.25	0.31	3	Rising	Yes

Fig. 18.

Comparison with previous designs: (a) Diagram of cells V.S. bits, (b) Diagrams of area V.S. bits, (c) Diagram of latency.

We will also face some limitations in the design of the shift register. Among them, we can refer to the topics of clock wiring and real implementation problems. Also, in the future goals of universal shift register design, it is also possible to consider reducing the area, designing in accordance with new clocking methods, and designing a testable universal shift register.

Ethics approval and consent to participate

Not applicable.

Consent for publication

Not applicable.

Availability of data and materials

The data that support the findings of this study are available from the corresponding author, upon reasonable request.

Funding

This work is based upon research funded by Iran National Science Foundation (INSF) under project No.4005782.

CRediT authorship contribution statement

Mojtaba Gholamnia Roshan: Writing – original draft, Software, Methodology, Investigation, Formal analysis, Conceptualization. Mohammad Gholami: Writing – review & editing, Validation, Supervision, Software, Project administration, Methodology, Investigation, Formal analysis, Conceptualization.

Declaration of competing interest

The authors declare the following financial interests/personal relationships which may be considered as potential competing interests:

Mohammad Gholami reports financial support was provided by Iran National Science Foundation. Mohammad Gholami reports a relationship with Iran National Science Foundation that includes: funding grants. If there are other authors, they declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Biographies

Mojtaba Gholamnia Roshan received the B·Sc. degree in Electronic engineering from Mazandaran Institute of Technology, Babol, Iran at 2011. From 2016 he has been an M.Sc. student at Mazandaran Institute of Technology, Babol, Iran. His research interests include digital design by emerging technologies, mainly on quantum-dot cellular automata (QCA), low power computer arithmetic.

Mohammad Gholami was born in Babol, Iran in 1986. He received the Ph.D. from the Babol Noshirvani University of Technology in 2014. From 2015 he has been a member of the Faculty of Engineering and Technology at University of Mazandaran. His current research interests include the design of RFIC integrated circuits, mixed-signal design and also digital design by emerging technologies, mainly on QCA.