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. 2024 Mar 8;14:5695. doi: 10.1038/s41598-024-56079-1

Table 2.

Neural networks’ architectures.

Encoder (E)
Layer No. filters Kernel size Strides Padding
3×Convolutional block 16 (3×3) (1×1) same
Max pooling (2×2) (2×2)
3×Convolutional block 32 (3×3) (1×1) same
Max Pooling (2×2) (2×2)
3×Convolutional block 64 (3×3) (1×1) same
Max Pooling (2×2) (2×2)
3×Convolutional block 128 (3×3) (1×1) same
Max Pooling (2×2) (2×2)
3×Convolutional block 256 (3×3) (1×1) same
Max pooling (2×2) (2×2)
Decoder (D, Daux)
Layer No. filters Kernel size Strides Padding
3×Convolutional block 256 (3×3) (1×1) same
Conv2DTranspose 128 (3×3) (2×2) same
Batch normalization
Activation: ReLU
3×Convolutional block 128 (3×3) (1×1) same
Conv2DTranspose 64 (3×3) (2×2) valid
Batch normalization
Activation: ReLU
3×Convolutional block 64 (3×3) (1×1) same
Conv2DTranspose 32 (3×3) (2×2) same
Batch normalization
Activation: ReLU
3×Convolutional block 32 (3×3) (1×1) same
Conv2DTranspose 16 (3×3) (2×2) valid
Batch normalization
Activation: ReLU
3×Convolutional block 16 (3×3) (1×1) same
Conv2DTranspose 1 (3×3) (2×2) valid
Batch normalization
Activation: ReLU
Conv2D 1 (3×3) (1×1) same
Batch normalization
Activation: sigmoid