Table 2.
Zed board FPGA resource utilization for backing crash prevention.
| Module | LUT | BRAM | DSP Slice |
|---|---|---|---|
| Interfacing modules (sensors, motors, Communication (UART), Xilinx IP cores) |
6852 | 24 | 36 |
| Static backing-up crash prevention @ perpendicular | 4788 | 8 | 10 |
| Static backing-up crash prevention @ Inclination | 5852 | 10 | 12 |
| Control unit and PWDC sensor fusion | 4468 | 20 | 42 |
| Partial Reconfiguration module | 5586 | 12 | 14 |
| Dynamic backing-up crash prevention @ perpendicular | 7448 | 16 | 12 |
| Dynamic backing-up crash prevention @ Inclination | 8512 | 18 | 14 |
| Total | 43,506 | 108 | 140 |