Fig. 4. Electrical performance of 2D multi-fin FinFETs based on aligned 2D Bi₂O₂Se-Bi₂SeO₅ fin-oxide arrays.

a Schematic diagram of 2D Bi₂O₂Se/Bi₂SeO₅/HfO₂ FinFET with three fins. b Cross-sectional STEM image of fin arrays. c–e Low-magnification STEM image (c), Energy-dispersive X-ray spectroscopy (EDS) image (d), and high-magnification STEM image (e) of Bi₂O₂Se/Bi₂SeO₅ fin-oxide heterostructures covered with HfO₂ dielectric layer. f Tilted SEM image of a 3-fin FinFET. g Typical output curves of the 2D multi-fin FET in (f). I_DS is the source-drain current. V_DS is the source-drain voltage and V_G is the gate voltage. L_ch represents the channel length of the devices. h Transfer curves of the 2D multi-fin FET in (f) and the repeated transfer curve measurement results for 50 cycles of the 2D multi-fin FET. I_G is the gate leakage current, V_th is the threshold voltage and ΔV_th means the shift of threshold voltage. The intersection of the two dashed lines is the threshold voltage of the device, represented by a solid line. i Statistical on-state current (I_ON) and off-state current (I_OFF) measured over 50 cycles for different multiple-channel 2D FinFETs. j, k Transfer curves (j) and statistical I_ON and I_OFF (k) of the 2D multi-fin FET in (f) operated under different temperatures. l Comparison of normalized current of the fabricated 2D multi-fin FETs with 2D MoS₂ FET⁴⁹, 2D InSe FET⁵⁰, 2D MoS₂ FinFETs²⁰ and Intel’s 14 nm-node Si FinFETs⁵¹ under low gate-voltage modulation. L is the channel length and W_eff is the effective width of device.