Fig. 2. Transistor-to-cell cooling efficacy.

a, b FET and PCB temperature evolution during in situ and ex situ operation for heating from 23 °C to 60 °C and − 30 °C to 5 °C, respectively. In situ, the large thermal sink of the cell prevents high FET temperature, which otherwise would rise rapidly toward safety limits. c Effective thermal resistance between the PCB/FET and thermal sink (ambient air for ex situ and cell average temperature for in situ). Here, T_∞ represents the effective heat sink temperature. T_FET and T_PCB represent the top and bottom heating sheet surface temperatures at the location of the FET, respectively. T_top and T_bottom represent the top and bottom cell surface temperatures in the center of the cell. The inset illustrates the heating sheet embedded in the center of the cell, where T_PCB is measured on the underside of the FET. See the Methods section for analysis details. Embedding the FET in the cell provides an order of magnitude reduction in thermal resistance to enable rapid and mutual thermal management for both the cell and FET. d Simulated temperature evolution during heating from 23 to 60 °C for a thermally optimized iSHB where the FET is in direct thermal contact with battery materials. e Effective thermal resistance for the cases in a and d. The simulation suggests direct thermal contact between the FET and battery materials can achieve an additional ten-fold reduction in thermal resistance. f Heat sink volume vs. thermal resistance off-the-shelf heat sinks that suit one of the most common power FET packages (TO-220) available from the two of the largest electronics distributors. The prototype iSHB cooling performance is comparable to these commercial circuit board FET heat sinks with a similar volume, and the simulation suggests even higher power dissipation is possible for the same allowable FET-to-cell temperature difference. Thus, using the battery as the heat sink could roughly halve the total system volume otherwise.