Table 2.
Classifier module architectures.
| Group Name | Input Size Output Size |
Block Structure (Kernel Size, Number) |
Block Number |
|---|---|---|---|
| Stage 0 | 1 × 384 1 × 96 |
1 × 7, 16 | 1 |
| Stage 1 | 1 × 96 1 × 32 |
1 × 7, 16 | 1 |
| Stage 2 | 1 × 32 1 × 32 |
1 × 1, 16 1 × 3, 16 1 × 1, 64 |
22 |
| Stage 3 | 1 × 32 1 × 16 |
1 × 1, 32 1 × 3, 32 1 × 1, 128 |
11 |
| Concatenation | 1 × 16 → 1 × 32 | - | - |
| Stage 4 | 1 × 32 1 × 16 |
1 × 1, 32 1 × 3, 32 1 × 1, 128 |
11 |
| Stage 5 | 1 × 16 1 × 8 |
1 × 1, 64 1 × 3, 64 1 × 1, 256 |
22 |
| Average pooling | 1 × 8 1 × 256 |
1 × 8 | 1 |
| Fully connected layer | 1 × 256 Class number |
- | 1 |