Table 2.
Extended Simulation results of the optimized E/E architecture for maximized BW constraint.
| Traffic | Src | Dst | BW [Mbps] | Protocol | Max Latency [µs] | Mean Latency [µs] | Max Jitter [µs] | Mean Jitter [µs] |
|---|---|---|---|---|---|---|---|---|
| Stream 0 | CF1 | ECU1 | 5 | AVB Class-A | 140.75 | 76.77 | 92.31 | 0.41 |
| Stream 1 | CF2 | ECU1 | 12 | AVB Class-A | 152.25 | 89.23 | 62.83 | 0.51 |
| Stream 2 | CF3 | ECU1 | 12 | AVB Class-A | 180.87 | 100.79 | 51.91 | 0.46 |
| Stream 3 | ML2 | ECU1 | 12 | AVB Class-A | 122.53 | 77.09 | 46.25 | 0.48 |
| Stream 4 | MR0 | ECU1 | 10 | AVB Class-A | 113.96 | 68.16 | 46.20 | 0.48 |
| Stream 5 | CR1 | ECU1 | 12 | AVB Class-A | 123.07 | 78.97 | 47.67 | 0.48 |
| Ctrl Traffic 0 | ECU1 | SBWR | 0.05 | TTEthernet | 315.11 | 314.06 | 0.93 | 0.24 |
| Ctrl Traffic 1 | ECU1 | SBWL | 0.05 | TTEthernet | 314.93 | 314.06 | 1.03 | 0.25 |