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. 2024 Aug 8;10(16):e35926. doi: 10.1016/j.heliyon.2024.e35926

Fig. 2.

Fig. 2

QCA gates: (a) majority gate with inputs (A, B, and C) and output (F); (b) AND gate with fixed cell (P = −1); (c) OR gate with fixed cell (P = +1); (d) a simple inverter on the same plane; (e) a simple inverter between different layers.