Fig. 4. Switching characteristics exhibiting nonvolatile memory of a Te nanowire self-gated ferroelectric field-effect transistor (SF-FET).

a Schematic showing the device structure. b R_ds–V_g characteristics for the Te nanowire and nanosheet SF-FETs (upper) and g_m–V_g hysteresis loop of Te nanowire SF-FET (lower). c Nonvolatile switching of R_ds measured after applying multiple V_p square pulses with the pulse width of 25 s, exhibiting multilevel resistive states. d Schematic showing polarization bound charge distribution with an external electric field applied and band structures for LRS and HRS at zero field. e R_ds–V_p hysteresis loops at V_ds = 0.5 V. Measurement of each data point is performed at V_g = 0 V after waiting for 1 min following applying each V_p pulse width of 20 ns, 100 ns, 1 μs, and 10 μs. f Nonvolatile resistive states switched by different V_p. Resistive states are measured after applying V_p pulses (from −100 V to 100 V then back to −100 V in steps of 10 V) of 100-ms width. The inset is the linear I_ds–V_ds characteristics after applying different V_p pulses labeled.