Table 1:

Comparison among reconfigurable on-chip schemes.

	Delay lines [24, 25]	Synthetic dimension [27]	Fourier transform [26]	Dot product [13, 21]	AWG (this work)
Number of fast modulated devices	1	N + 1	M + N − 1	M	N
Number of slow modulated devices	M	0	M + N − 1	M	M
Total number of modulated devices	M + 1	N + 1	2 × (N + M − 1)	2 × M	M + N
Number of clock cycles	N + M − 1	N/A	1	N + M − 1	1
Product of modulated devices and clock cycles	(M + 1) × (N + M − 1)	N/A	2 × (N + M − 1)	2 × M × (N + M − 1)	M + N