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. 2024 Dec 1;14(23):1936. doi: 10.3390/nano14231936

Figure 3.

Figure 3

The dynamic behavior of the nonvolatile gate charge-trap memory based on MoS2/PdSe2 heterostructure: (a,b) Ids–VG characteristics of the device under different VG under the forward bias of −1 V and reverse bias of +1 V, respectively; (c,d) Ids–Vds characteristics of the device under different pulse durations and amplitudes.