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. 2024 Dec 19;14(24):2036. doi: 10.3390/nano14242036

Figure 2.

Figure 2

The schematic of the proposed SERS chip, which consists of a 3-layer structured thin film system constructed on a silica substrate. The thickness of the upper and lower layers containing gold t = 50 nm, the thickness of PMMA film h = 120 nm, the diameter of the nanohole is d, and the period p = 315 nm.