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. 2024 Dec 30;15:10809. doi: 10.1038/s41467-024-55077-1

Fig. 5. Achieving high-gain and low-noise cryogenic electronics using III-V on Si devices.

Fig. 5

fT versus IDgm1 (a) and fT versus PDC (b) benchmarks for state-of-the-art cryogenic RF transistors. The fT and IDgm1 are extracted at each optimum bias point, not at the same bias. Among the presented devices, our device is closest to the optimum corner region (highest fT and lowest noise indication factor & highest fT and lowest PDC). Inset includes fT versus IDgm1 benchmark only for III-V. Data from refs. 18,20,21,4750. c Projected power consumption profiles for our device and CMOS depending on the number of gates and considering the presence or absence of routing circuits. The routing ratio is 1-to-10. Colored lines indicate the cooling power achievable with state-of-the-art dilution refrigerators, assuming 50% power consumption at the readout.