From Printed Devices to Vertically Stacked, 3D Flexible Hybrid Systems

Abstract

The pursuit of miniaturized Si electronics has revolutionized computing and communication. During recent years, the value addition in electronics has also been achieved through printing, flexible and stretchable electronics form factors, and integration over areas larger than wafer size. Unlike Si semiconductor manufacturing which takes months from tape‐out to wafer production, printed electronics offers greater flexibility and fast‐prototyping capabilities with lesser resources and waste generation. While significant advances have been made with various types of printed sensors and other passive devices, printed circuits still lag behind Si‐based electronics in terms of performance, integration density, and functionality. In this regard, recent advances using high‐resolution printing coupled with the use of high mobility materials and device engineering, for both in‐plane and out‐of‐plane integration, raise hopes. This paper focuses on the progress in printed electronics, highlighting emerging printing technologies and related aspects such as resource efficiency, environmental impact, integration scale, and the novel functionalities enabled by vertical integration of printed electronics. By highlighting these advances, this paper intends to reveal the future promise of printed electronics as a sustainable and resource‐efficient route for realizing high‐performance integrated circuits and systems.

Printed electronics, with their extensive versatility, resource efficiency, and fast‐prototyping capabilities, offer an attractive alternative to Si‐based CMOS technology. This paper reviews the recent advances in printed electronics, highlighting emerging printing technologies that could lead to high performance, as well as attributes such as resource efficiency, environmental impact, integration scale, and vertical stack leading to 3D integration.

1. Introduction

Achieving smaller and faster transistors has been a key goal of the semiconductor industry for more than half a century, which fostered numerous breakthroughs in several areas: starting from space missions to widespread use of the internet, the weather and disaster forecasting, defense and homeland security, the autonomous vehicles, robotics, universal AI, and more.^{[ 1 ]} The growth in these fields is underpinned by the ultrafast computing and communication provided by modern Si CMOS electronics. Yet, as revolutionary as these advances have been, the way the current electronics are manufactured is not eco‐friendly, as there is heavy reliance on resource‐intensive and environment‐unfriendly processes such as lithography and etching. Current semiconductor manufacturing processes require large amounts of energy, water, scarce critical raw materials (CRMs), and large floor areas and release considerable toxic chemicals as byproducts – all of which adversely affect the ecosystem and human health.^{[ 2 ]} Even at the high environmental cost, the Si CMOS technology cannot meet all the needs of fast‐growing applications such as wearables, electronics skin, etc., where flexible form factor is critical.^{[ 3 ]} A more sustainable, resource‐efficient, and versatile approach is needed to address the above gaps while meeting the needs of the emerging applications.

Printed electronics is a new way of making and using electronics. Unlike lithography‐based processes, the additive, drop‐on‐demand nature of printing techniques eliminates most of the material subtraction in manufacturing, with much lower energy, water, and chemical solvent consumption. In this regard, printed electronics hold great promise for resource‐efficient and environmentally friendly manufacturing. On the other hand, printed electronics are also versatile, showing the capability to cover a larger area beyond the limit of the wafers currently in use for CMOS electronics. The possibility to process printed layers at low temperatures makes this technology compatible with various unconventional substrates that facilitate mechanical flexibility, stretchability, and even degradability at the end of life.^{[ 4 ]} Such novel manufacturing technology offers exceptional potential and opens new avenues for various applications including the internet‐of‐things, healthcare monitoring, robotics, optoelectronics, and prosthetics.^{[ 5 ]} However, the current printed electronics market is still mostly limited to passive devices such as various types of sensors, interconnects antenna, etc., developed using different types of functional inks or as part of heterogeneous integration with conventional Si CMOS;^{[ 6 ]} the attempts to develop printed active circuits are largely limited to the laboratory scale, offering modest performance. Improvement of important device metrics, including contact resistance, line feature resolution, switching frequency, and device density is required.^{[ 7 ]} As it stands, most of the metrics offered by printed electronics are several orders of magnitude lower than that of the Si CMOS, and therefore the printed devices and circuits are mainly limited to the low‐end application.^{[ 8 ]}

The market demand for multifunctional large‐area electronic systems necessitates the integration of different functional blocks that require a large number of transistors working collectively, which is in sharp conflict with the bottleneck in device density offered by printing. Similar problems have long been encountered in Si‐based CMOS where the exploration of the vertical dimension has proven to be an effective solution.^{[ 9 ]} Depending on the number of layers stacked in the vertical dimension, the number of devices accommodated in a unit area could be increased many times over. This also allows for a reduced layout complexity, smaller power consumption,^{[ 10 ]} compact packaging (e.g., using thinned chips),^{[ 11 ]} and provides a natural platform to carry out the heterogeneous integration of electronics made of different materials.^{[ 12 ]} A comparable 3D integration strategy is likely to emerge as a potential solution to tackle the density inefficiency in printed electronics,^{[ 13 ]} supported by developments such as printed interconnects for hetero‐integration, printed encapsulation, and vias, etc.^{[ 14 ]} Exploring the out‐of‐plane space also offers opportunities to broaden the capabilities of the printed electronics by integration of various functional blocks, and to enable new functionalities that are otherwise unattainable by printed electronics or traditional methods alone. This review article covers the recent advances in printed electronics, where resource efficiency, high performance, and high integration density (i.e., achieved through 3D integration) are highlighted along with sustainable and eco‐friendly manufacturing. The discussion here complements the previous review articles in printed electronics that have focused on different aspects such as printed sensors and sensing interfaces,^{[ 6} , ^{15 ]} printing chemistry and materials,^{[ 16 ]} specific printing technologies,^{[ 17 ]} printed circuits and systems,^{[ 18 ]} and many more.^{[ 19 ]}

The structure of this paper follows the above arguments, starting with Section 2 presenting a historical overview of the development of conventional Si CMOS and printed electronics, and how they proceed from 2D to 3D through heterogenous integration as intermediate steps reflecting their convergence. Section 3 reviews the available printing technology, primarily focusing on those holding potential for the development of high‐performance electronics and large‐scale integration. Section 4 discusses the challenges that are faced in upscaling printed electronics for large areas as well as 3D stacking. Progresses in the design and simulation, fabrication and integration, performance and resource‐efficiency, functionality, and yield, have also been highlighted in this section. Section 5 explores the novel functionalities of 3D integration in hybrid to fully printed electronics, including the 3D stretchability and functionality control in 3D transient electronics. In this work, the fully printed electronic system refers to the entire electronic system that is realized by printing whereas the hybrid system refers to the integration of printed electronics and non‐printed electronics (for example, off‐the‐shelf components). One typical example of a fully printed system can include a printed energy harvester, printed capacitor, printed sensors printed thin‐film transistors, and printed antenna, as illustrated in ref. [20] By reviewing the recent progress in printed electronics and its progress from 2D to 3D, this review paper hopes to attract more interest from scientists and practitioners of every stage working in printed and flexible electronics, toward this resource‐efficient and eco‐friendly semiconductor manufacturing, while delivering high‐performance and large‐scale integration.

2. Planar to 3D Electronics

Going back to the 1940s, one would be astounded by the gigantic size of the vacuum tubes that were in use for computing. The first generation of computers such as ENIAC was built using ≈20,000 vacuum tubes, occupying a floor area equivalent to half the size of an NBA court. Then in 1947, the point‐contact transistor from Bell Labs changed the course with transistors having a channel length of ≈40 µm.^{[ 21 ]} Thereafter, researchers have persistently sought ways to further miniaturize these fundamental building blocks of electronics. The advancement in transistors’ dimensional downscaling was predicted by Gordon Moore when he articulated the famous Moore's Law in 1965:^{[ 1b ]} the number of transistors on an integrated circuit would roughly double every two years (then revised to every 18 months). In the following decades, significant progress has been made, culminating in transistors with channel lengths now measured in a few nanometres (Figure 1 ). However, approaching the nanoscale inevitably brings quantum effects into play: the increase in tunneling currents through the gate oxide makes it increasingly difficult to turn off transistors completely. The dimensional scaling of individual transistors is approaching its physical limit. The introduction of the ultra‐thin gate oxide dielectric further exacerbated the issue. In this regard, the use of FinFET structure is attractive as it provides superior electrostatic control of the channel region compared to the planar gate control in MOSFETs. Such a device structure innovation enables further physical downscaling. While FinFET structure was proposed in ≈2000, other new architectures, such as Gate‐All‐Around NW FETs, gate‐all‐around (GAA) stacked Nanosheet FETs, etc., that have also appeared in the past decade enable better electrostatic control.

Figure 1.

The progress of conventional Si CMOS and printed electronics, and their respective advancement from 2D to 3D. The lower two sub‐branches (in blue color) show the development of Si CMOS technology and 3D Si CMOS integration; the top two sub‐branches (in green color) show the development of printed electronics and printed 3D electronics. The example figures on the top show the representative work in printed electronics and printed 3D electronics. The source of the example figures is detailed as follows: 1 Reproduced with permission.^{[ 31 ]} Copyright 2011, American Association for the Advancement of Science. 2 Reproduced with permission.^{[ 32 ]} Copyright 2006, American Association for the Advancement of Science. 3 Reproduced with permission.^{[ 33 ]} Copyright 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim. 4 Adapted with permission.^{[ 29g ]} Copyright 2012, American Association for the Advancement of Science. 5 Adapted with permission.^{[ 34 ]} Open access. 6 Adapted with permission.^{[ 35 ]} Copyright 2024, The Author(s), under exclusive license to Springer Nature Limited.

A logical approach to further enhance the device density but avoid tackling the quantum effects is to explore vertical integration. First proposed in the 1980s,^{[ 22 ]} the Si CMOS technology has gradually witnessed a paradigm shift from planar (i.e., a 2D layout where transistors, resistors, capacitors, and interconnects are on the same plane) to 3D. At present, while researchers are still in pursuit of smaller transistors, exploiting the vertical space seems to provide more gains for the future advancements of electronics. The concept of “3D integration” has evolved into a broad family, all of which can be described as either parallel integration or sequential integration. Parallel 3D integration refers to a scenario where several groups of electronics are fabricated individually and then integrated vertically to create a 3D layout, including 3D system in package (3D SIP), 3D wafer‐level packaging (3D WLP), and 3D stacked ICs (3D‐SICs). Typical examples include the high‐end processors from Apple (e.g., M1 Ultra processor), Nvidia, and AMD (e.g., EPYC 9004 processor). However, the 3D packing too has a limit in terms of integration density because of technical obstacles such as substrate misalignment from the wafer bow.^{[ 23 ]} Sequential 3D integration is another name for monolithic 3D,^{[ 24 ]} i.e., sequentially fabricating electronic layers on the same substrate, from the bottom to the top. Unlike 3D packaging, this approach enables the creation of a system with higher device (via) density. Typical examples include the 3D monolithic chip from Intel,^{[ 25 ]} Imec,^{[ 26 ]} and more. 3D integration also offers possibilities to finely adjust the performance of each type of device. This can be achieved by separating different types of devices into different layers and optimizing the substrate properties (e.g., orientation) to suit the device's performance.^{[ 27 ]}

While planar Si CMOS technology and 3D integration advanced electronics through miniaturization following Moore's Law, the demands for versatile applications such as sensing, actuating, radio frequency communication, etc, also pushed the semiconductor research toward more functionalities. This “More than Moore” concept not only requires the use of novel materials and innovative device architectures but also new manufacturing techniques that can accommodate the fabrication on unconventional substrates (Figure 1). Here, printing technologies are attractive as they offer inherently resource‐efficient and eco‐friendly manufacturing routes for electronics. Unlike lithography‐based conventional subtractive process, drop‐on‐demand printing uses as many resources as needed and hence inherently minimizes the waste associated with the fabrication.^{[ 28 ]} This is becoming increasingly important because of the size and impact of the electronic industry on various sectors and the considerable amount of electronic waste that is becoming increasingly difficult to manage. The development of printed electronics also fosters the emergence of transient and compostable electronics: the devices that are designed to function for a prescribed period and disintegrate/degrade afterward into useful byproducts.^{[ 29 ]} This feature is particularly attractive for electronic products that are meant to be used once or a few times (e.g., disposable sensors for health applications).^{[ 30 ]} The transient electronics in many scenarios can fully fulfill the users’ requirements while creating a minimum burden on the environment.

Despite numerous pioneering efforts in the field, the advancement of printed electronics remains significantly constrained by key performance metrics, such as field‐effect mobility and contact resistance, along with factors like long channel lengths, low integration density, and modest switching frequencies at best.^{[ 36 ]} These features limit the use of current printed electronics to low‐end applications (e.g., sensing and display). Without tackling these fundamental issues, it will be a formidable challenge for printed circuits to become an alternative option for the Si‐based CMOS circuits even for the mid‐end applications. To this end, the researchers have already started to explore hybrid manufacturing (i.e., use of both printing and non‐printing methods in developing devices) or heterogeneous integration of rigid electronic components based on conventional CMOS processes with printed, flexible passive/active electronics (i.e., flexible hybrid electronics) to bridge the above gap. The hybrid fabrication strategy makes it possible to take advantage of a certain degree of flexibility and versatility offered by the printing technology, while still utilizing the mature standard micro‐ and nanofabrication technology to ensure high performance. Various works have been done in the past, including printing only semiconductors,^{[ 37 ]} printing only dielectrics,^{[ 38 ]} printing only the metal contacts,^{[ 39 ]} printing both contacts and the elastiff layer (for stretchable electronics),^{[ 40 ]} and more. In a broader sense, many advances in nanoelectronics can be seen as adopting a hybrid fabrication approach and holding potential for resource‐efficient, lithography‐free electronics.^{[ 41 ]} Heterogeneous integration enabled by flexible hybrid electronics (FHE), on the other hand, integrates mechanically flexible electronic components made from printed electronics (e.g., flexible sensors) and the rigid components fabricated by standard micro‐ or nanofabrication processes (e.g., processing hardware). This strategy also takes advantage of both printing and standard manufacturing but at the system level. This aspect will be discussed in Section 4.4.

Owing to technological limitations such as low‐resolution of printed structures (ca., micron scale) achievable with today's printing tools, current printed electronics technology is better suited for large‐area electronic applications such as displays and sensing (e.g., whole‐body electronic skin for robots).^{[ 6} , ^{42 ]} While this complements the current chip‐based approach, the feature size of printed electronics is persistently getting smaller; we also see layer‐by‐layer stacked, printed 3D systems, just as the way that traditional silicon CMOS technology transitioned from planar to 3D. The exploration of printed 3D electronics emerged in the 2000s, encompassing both organic and inorganic semiconductors.^{[ 32} , ^{33 ]} The term printed 3D electronics in this work refers to printed active devices (mainly field‐effect transistors) integrated over the vertical dimension. This strategy offers a significant increase in areal density without encountering the challenges associated with downsizing device dimensions. Unlike traditional electronics where thermal budget mismatch poses a significant hurdle, the low‐temperature processing inherent in printed electronics naturally lends itself to 3D integration. For example, in Si technology, thermal activation of dopants is typically achieved at high temperatures (600–1000 °C). This is significantly higher than the thermal budget allowance of the interconnects (e.g. Cu) and interlayer dielectric. This makes monolithic 3D integration challenging. Possible solutions include local laser annealing,^{[ 43 ]} solid phase epitaxy (SPE),^{[ 44 ]} and others. Apart from the contact issue, the dielectric/passivation deposition also typically requires high temperature (e.g. thermal growth of SiO₂ at 1000 °C). This can be replaced by other deposition methods such as ALD (atomic layer deposition) at a much lower temperature to enable 3D integration.

The thermal budget mismatch is also a challenge for printed electronics and their 3D integration, but this is far less severe compared to the case of Si technology or direct integration on flexible substrates. Printing technology inherently allows the deposition of various materials (e.g. metal, semiconductor, dielectric) for electronics at low temperatures. Normally the deposited ink only requires sintering at moderately elevated temperatures, for example, to remove organic additives and stabilizers to prevent aggregation. Thermal sintering is often performed at a temperature in the range of 150–250 °C. This is still in conflict with the thermal budget of many polymeric substrates as they have lower glass transition temperatures. For example, the glass transition temperature of PET (polyethylene terephthalate) is 70–100 °C, for PEN (polyethylene naphthalate) 120–155 °C, and for PI (polyimide) 155–270 °C. Thermal processing of printed electronics above glass transition temperature will result in degradation of the polymer film. Possible solutions include the use of other sintering techniques that do not require high temperatures, such as intense pulsed light sintering,^{[ 45 ]} UV sintering,^{[ 46 ]} microwave flash sintering,^{[ 47 ]} plasma sintering,^{[ 48 ]} and others.^{[ 49 ]} Achieving printed 3D integration usually does not impose any further thermal budget limitation because depositing interconnects to make electrical connections to already fabricated devices (BEOL equivalent) would have a similar thermal budget as fabricating devices layer by layer (FEOL equivalent). This is a distinct advantage for printed electronics when it comes to 3D integration.

Although the future trajectory of printed electronics remains an open question, the incorporation of 3D integration in printed electronics is expected to lead to a higher areal density. With the capability of integration over a large or very large scale, printed electronics could offer more advanced functionality on various conventional and unconventional substrates and provide sustainable manufacturing opportunities such as more resource efficient, reduced toxic waste, and improved cost‐effectiveness. Some of these advanced printing technologies are discussed in the next section.

3. The Resource‐Efficient Fabrication

The current semiconductor manufacturing has high adverse environmental impacts since it involves the use of large quantities of raw material, water, energy, and the generation of waste and emissions.^{[ 50 ]} Photolithography, which is a critical step for the fabrication of conventional ICs, deposits layers of semiconductors, dielectrics, and metals–a big part of which is removed via photoresist patterning and etching steps to obtain desired structures. With techniques such as deep UV (DUV) and extreme UV (EUV) lithography, liquid immersion lithography, etc., traditional IC manufacturing has achieved extraordinary successes in terms of high‐density, and fine features down to a few nanometers.^{[ 51 ]} This process step, however, is inherently wasteful as an enormous amount of toxic waste including chemicals, heavy metals, etc. is generated, with considerable adverse environmental impact.^{[ 50} , ^{52 ]} For example, the adoption of double patterning techniques by fabs to maintain the sophistication of mask features caused a spike in the wastage levels in 2013.^{[ 53 ]} Photolithographic chemicals, such as perfluorooctane sulfonate (PFOS) and tetramethylammonium hydroxide (TMAH), increase the toxicity of the wastewater. Many Si chip fabs struggle to meet their self‐imposed TMAH contamination limits,^{[ 50} , ^{52 ]} which spurred the introduction of on‐site waste material reclamation and recycling facilities in 2015.^{[ 54 ]} Although such waste management measures are laudable, most chemicals extracted by semiconductor foundries from wastewaters are not reintroduced on‐site but downcycled to industrial buyers outside the semiconductor sector. The recovery and purification of economically viable materials is possible only with the help of chemical additives,^{[ 55 ]} or energy‐intensive processes such as reverse osmosis.^{[ 56 ]} While serving a circular economy agenda, such recycling activities still increase the environmental footprint of an already high‐impact industry.

As mentioned earlier, conventional semiconductor foundries consume vast quantities of resources. For instance, water is used during chip manufacturing for a variety of purposes ranging from equipment cooling to wafer surface cleaning. Particularly, ultrapure water (UPW) is required for process steps, such as wet etch, solvent processing, and chemical mechanical planarization/polishing (CMP). According to the International Technology Roadmap for Semiconductors (ITRS), device fabs utilize ≈7 L cm⁻² of UPW per wafer.^{[ 57 ]} The large semiconductor fabs also consume notable energy and the figure is increasing over time. As an example, in 2020, a unit energy consumption of 26.7 kWh per 12‐inch wafer equivalent mask layer was reported.^{[ 58 ]} The extreme resource demands of CMOS processing, along with the need to have large and centralized electronics manufacturing foundry to carry out the process, potentially put the continuity of IC foundries and their global supply chain partners at risk.^{[ 59 ]} To this end, it is beneficial to have an alternative electronics manufacturing strategy and supply chain that is designed to be smaller but is widely distributed and operates in a more resource‐efficient manner with low installation/fabrication costs. Printing technology is additive, and many techniques can operate on a drop‐on‐demand basis, leading to maskless digital manufacturing. This results in minimal chemical waste during manufacturing and lower fabrication costs. The smaller but resource‐efficient printed electronics fabs could enable decentralized electronics fabrication and greater sustainability.

Broadly speaking, printed technologies can be divided into two categories i.e., wet and dry printing.^{[ 15 ]} Conventional (wet) printing techniques such as inkjet, gravure, etc. have been explored to print various organic or inorganic materials. These techniques offer relatively large feature resolution (in the range of tens of micron meters or larger) but are more mature. For example, screen printing has been widely used in the printed electronics industry for sensor fabrication.^{[ 64 ]} Likewise, inkjet printing has been used for a range of applications including sensors, energy devices, and small‐scale circuits.^{[ 65 ]} While these printing methods offer several advantages, they also present several shortcomings including nozzle clogging, contamination, lower registration accuracy, and process‐to‐process and device‐to‐device variations.^{[ 66 ]} These techniques have been extensively covered in previous reviews.^{[ 15} , ^{67 ]} It should also be noted that the advances in wet printing techniques also fostered the development of additive manufacturing, which allows the realization of more complicated structures in 3D. Although this may not guarantee an increased device density, the freedom offered by the constructing components in all three dimensions is advantageous for many applications such as wearable electronics and sensors,^{[ 68 ]} soft robots,^{[ 69 ]} energy storage,^{[ 70 ]} healthcare and medicals,^{[ 71 ]} consumer electronics,^{[ 72 ]} and more. Particularly, sensors have been realized by additive manufacturing methods as may be noted from previous review papers in this field.^{[ 73 ]}

Various techniques developed for additive manufacturing (e.g., fused deposition modeling, digital light processing, and two‐photon polymerization, etc.) have their advantages and disadvantages. For example, fused deposition modeling employs materials such as thermoplastic polymers as printing filaments and is cost‐effective. However, it usually leads to a low printing resolution and rough surface. Digital light processing is advantageous in feature resolution and processing speed owing to the use of a digital light projector for spatially controlled solidification.^{[ 74 ]} However, it requires certain post‐processing steps and is limited by the choice of material to be printed. Two‐photon polymerization, which employs the physical effect of two‐photon absorption, allows for the creation of complex structures in the nanoscale.^{[ 75 ]} However, the requirements such as femtosecond laser setup make this technique expensive. A detailed review of this area can be found in previous publications.^{[ 76 ]}

A few novel wet printing techniques, that have emerged in the last decade or so, allow printed feature sizes down to the micron and even submicron scale in some cases. Taking advantage of the high electric fields, electrohydrodynamic (EHD) printing can overcome the surface tension and viscous force in the extrusion process, allowing the ejection of super‐fine droplets.^{[ 77 ]} High‐precision capillary printing (HPCAP), instead, leverages the capillary force and resonance to manipulate the flow of the ink, like the mechanism of the fountain pen.^{[ 78 ]} The ultraprecise dispensing (UPD) technology‐based printer uses a high‐precision pump and associated motion control system, to dispense the microliter level of fluids.^{[ 79 ]} This technique allows for the printing of highly viscous inks, thus holding greater potential for printing vertical structures. These emerging high‐resolution printers also offer exciting opportunities for the fabrication of FETs with sub‐micron channel length. This would be equivalent to the device dimensions produced by conventional lithography‐based approaches in the late 1980s and early 1990s. While the research into minimizing printed devices continues, there is a clear need to further increase the density of printed devices, and this is where 3D integration comes in, as discussed in Section 2.

On the other hand, dry printing employs van der Waals (vdW) force to transfer the material‐of‐interest from the donor to the recipient substrate. These techniques are gaining attention as they allow fabrication of active devices/circuits with performance on par with Si‐based conventional electronics, using inorganic nanostructures of Si, Ge GaAs, InGaAs, and more (Figure 2a–c).^{[ 27} , ^{80 ]} For example, laser printing, termed laser‐induced forward transfer, employs laser radiation to a donor substrate to transfer the donor material to the receiver substrate underneath.^{[ 81 ]} The printing resolution of this technique is determined by several factors including the dimension of the laser beam and its intensity distribution, the laser pulse duration, the property of the material‐to‐be‐transferred, and more. Sub‐micrometer printing resolution has been successfully achieved and the technique has been widely used for the realization of various electronic devices.^{[ 82 ]} Other printing techniques (i.e., transfer printing, contact printing, and direct roll printing) also exist but they may require additional lithography steps to complete the device fabrication. Recently reported dry‐printing approaches such as in‐tandem contact‐transfer printing (Figure 2d) and selective removal (Figure 2e) require one lithography step to prepare the master template for nanomaterial patterning, but the developed master template can be reused multiple times. The selective transfer and selective removal of nanomaterials in this case are equivalent to the outcome of positive and negative photoresists in conventional chip fabrication. In this regard, this method is more resource‐efficient and environment‐friendly. While the resolution of printed nanostructures depends on the lithography process (or lithography‐created molds), the alignment resolution of the nanostructure obtained from different prints is also important. To this end, an automated process has been developed to enable dry printing alignment accuracy down to hundreds of nanometer scale.^{[ 83 ]} This is similar to what can be achieved by the state‐of‐the‐art wet printing tools. Table 1 presents a comparison of several manufacturing techniques used in semiconductor manufacturing.

Figure 2.

Schematic illustration of the lithography‐assisted dry printing techniques for area‐selective printing of nano‐to‐chip scale inorganic structures: a) direct roll printing, which holds potential for R2R (Roll‐to‐Roll), high‐throughput fabrication of flexible electronics.^{[ 37a ]} b) Contact printing of vertically aligned structures such as nanowires and nanotubes. The process mainly uses the van der Waals force generated during the contact between the donor and receiver substrates to detach (break) the nanostructures from the donor and uses the horizontal shear forces generated during sliding to directionally align these nanostructures on the receiver.^{[ 60 ]} c) Transfer printing using elastomeric stamps.^{[ 61 ]} The concept is inspired by micro‐contact printing, which was initially explored to address flexible electronics manufacturing challenges, such as thermal budget constraints, encountered when employing conventional microfabrication processes on inherently flexible substrates. The method is applicable to transfer materials and structures from nano‐to chip‐scale.^{[ 62 ]} In the scheme, tiny chips (<10 mm) of diverse components such as transistors, sensors, capacitors, etc. made using different process nodes, materials, and technologies were picked and placed in a 2D layout for heterogeneous integration. In this paper, the 2D layout refers to the integration of active and passive devices (transistors, resistors, capacitors, interconnects) on the same plane. d) in‐tandem contact‐transfer printing to selectively align quasi‐1D materials such as NWs.^{[ 29a ]} It is a two‐step process developed to address the limitations of both transfer and contact printing methods. This approach is equivalent to conventional additive manufacturing and offers considerable advantages in terms of resource efficiency, cost‐effectiveness, and eco‐friendliness, by avoiding repeated use of conventional lithography steps. e) selective removal.^{[ 63 ]} The selective removal approach starts with the deposition of a nanoscale electronic layer uniformly over an entire substrate area. Later, the printed nanoscale layer is selectively removed from pre‐selected locations (unwanted areas) utilizing a patterned PDMS stamp. This approach is equivalent to the conventional negative photolithography process. The trench‐patterned PDMS stamps are fabricated by curing a layer of PDMS on top of the master Si substrate patterned with negative photoresist relief structures following the conventional microfabrication process steps. This is the only step that requires a lithography process, and the Si mold can be reused afterward. To enhance the yield of NW removal, a similar capillary‐force‐assisted technique was adopted in which the PDMS stamp was exposed to water vapors to improve its adhesive capability. After contact, the PDMS stamp was lifted from the substrate having the NW‐based electronic layer.

Table 1.

A comparison of printing techniques against traditional lithography‐based fabrication techniques.

Parameter	EUV lithography	High‐resolution wet printing	Transfer printing	Contact printing	Direct roll printing	In tandem contact transfer printing	Selective removal
Principle of operation	Reflection of light of 13.5 nm wavelength	Electric field assisted/meniscus guided, and more	The competing interfacial adhesion between the structure/donor and stamp/structure	Shear forces for alignment, van der Waals force for adhesion.	van der Waals force	Shear force and van der Waals force	Shear force and van der Waals force
Tool complexity and cost	Complex multilayer optics, and high vacuum. Cost of tool > $30 million.	Low to medium; Cost of tool≈$100 k	Low to medium; Cost of tool≈$100 k	Low complexity. Tool not commercialized	Low to medium complexity. Tool not commercialized	Low to medium complexity. Tool not commercialized	Low to medium complexity. Tool not commercialized
Lithography requirement	Multiple photolithography and masks needed	Not needed	Needed during the nanomaterial fabrication step	Needed for selective printing of nanomaterials.	Needed during the nanomaterial fabrication step	Needed to make the master template	Needed to make the master template
Resolution	Resolution down to nanometer.	Resolution down to submicron‐meter.	Micro‐ and nano‐meter scale depends on donor materials.	Depends on donor materials, defined by material synthesis.	The micrometer scale depends on donor materials.	Depends on donor materials, defined by material synthesis.	Depends on donor materials, defined by material synthesis.
Environmental consideration	Use of chemicals throughout the process, ≈200 kg/wafer m2 of hazardous waste	Chemical use in making the ink,	Chemical use in defining donor materials/structures.	Chemical use in selective printing.	Chemical use in defining donor materials/structures.	Chemical use in making the master template.	Chemical use in making the master template
Ref.	[50, 84]	[78a]	[41b]	[60]	[37a]	[29a]	[63]

4. 3D Integration for Upscaling Printed/Hybrid Electronics

The printing technology discussed in the previous section has fostered advances in printed electronics. This section focuses on the transistors and circuits realized following either a fully printed or a hybrid (partially printing) method, along with their heterogeneous integration. The challenges encountered in realizing 3D‐integrated printed and hybrid electronics, as well as the efforts dedicated to them have also been covered.

4.1. Design, Layout and Simulation

To upscale the technology (e.g. toward LSI and VLSI) and facilitate the industrial uptake of printed electronics, it is essential to develop process design kits (PDKs) providing all the necessary information and guidelines for sectors in the semiconductor design and manufacturing pipeline. In conventional electronics, the PDKs need to contain information for: 1) understanding the influence of the manufacturing process on device performance; 2) compact device‐level modeling. 3) layout design rules; 4) circuit‐level simulation (i.e., SPICE model); 5) standard cell libraries; 6) verification checks, and more. Particularly, to develop an advanced SPICE model (level 3 or above), the noise behavior should be studied and incorporated. For printed FETs, the types of noise generally include flicker noise, thermal noise, etc. Flicker noise is mainly caused by the charge carrier trapping and de‐trapping process owing to the channel‐dielectric defects. The power spectrum density of flicker noise usually shows the dependency of 1/f, where f is the frequency of the noise fluctuations. The strategies suggested to minimize the flicker noise in various material systems include reducing the interfacial trap density of states for printed organic FETs.^{[ 87 ]} Thermal noise, on the other hand, is due to the random thermal movement of charge carriers. Its power spectrum density shows a flat band for different frequencies. Owing to the different frequency behavior, flicker noise dominates in the low‐frequency range while thermal noise dominates in the high‐frequency range. Noise in electrical components is a stochastic process. To realize high‐performance analog circuits (e.g., amplifiers) using printed electronics, understanding and modeling their noise behavior is required. However, the relevant research is still in its infancy and more attention is needed.^{[ 87} , ^{88 ]}

The development of PDKs for printed electronics presents unique challenges compared to traditional Si CMOS technologies due to several factors: 1) there is a vast number of available materials that can be printed, including organic semiconductors, carbon nanotubes, nanowires, metal oxide thin films, 2D materials, and more, each with different electrical properties such as carrier mobilities, defect densities, electron affinity, and environmental stability; 2) Even for the same material, there is number of different printing tools are available and often they follow distinct printing mechanisms. As a result, designers must face different technological constraints, and deal with different design rules for materials printed using these methods. For example, minimum line width and line spacing rules have been developed for inkjet printing technology;^{[ 85 ]} To achieve correct pattern printing, specific compensation rules have also been developed by taking into account the flowing nature of the printed ink (Figure 3a). The first and second limitations listed here almost dictate the need to design individual PDKs tailored to each material or/and printing strategy; 3) printed electronic devices often reside on non‐traditional substrates, such as bendable, stretchable, or biodegradable materials. As a result, device and circuit‐level models must account for substrate effects. For example, if the designed devices and circuits are printed on flexible substrates, then it is also essential to consider the variations in the charge carrier mobility values due to the piezoresistive effect or the strain experienced during bending;^{[ 89 ]} 4) there are more random factors that affect manufacturing and manifest themselves in device performance variations. To address this, strategies such as the Monte Carlo method, and Worst‐Case Analysis should be incorporated. Despite these challenges, notable progress has been made in PDK development for novel material‐based electronics (Figure 3b). To name some representative examples: PDKs have been developed for printed organic‐based and metal‐oxide‐based transistors,^{[ 90 ]} for electrolyte‐gated transistors based on both organics and CNTs (carbon nanotubes),^{[ 91 ]} for organic semiconductor transistors,^{[ 92 ]} for flexible hybrid electronics,^{[ 93 ]} and for gravure printed organic TFTs.^{[ 94 ]} These pioneering works reflect the ongoing efforts to advance printed electronics from the device level to the circuit level.^{[ 19} , ⁸⁶ , ^{95 ]}

Figure 3.

The PDK development for printed electronics. a) (Left) The design and actual inkjet printer inks in the scenarios with and without compensation. (Right) Different compensation strategies for the same notch shape design. Reproduced with permission.^{[ 85 ]} Open access. b) The scheme shows the development of PDKs for printed electronics. Reproduced with permission^{[ 86 ]} Copyright 2019, IOP Publishing.

When it comes to 3D integration, additional benefits and considerations prevail. For example, by exploring the vertical dimension, the circuit layout can be redesigned for reduced complexity and improved performance.^{[ 96 ]} While this aspect has been widely studied in Si CMOS, the progress in 3D printed/hybrid electronics is still in its infancy.^{[ 97 ]} Considering this, the inspiration for the design of printed 3D electronics can be drawn from conventional lithography‐based (or hybrid) electronics. For example, a shared gate configuration arranged in 2‐tiers has been extensively explored in both forms of electronics, in various material systems including CNTs, TMDs, organic semiconductors, etc (see Figure 4a).^{[ 98 ]} Other 2‐tier logic gates, such as NAND, NOR, SRAM, 1‐bit full adder, etc, have also been realized using the shared gate configuration. This allows up to 40% area reduction (Figure 4b).^{[ 99 ]} Subsequent research indicates that a 3‐tier layout in combination with a bottom gate device structure within a 2D material‐based system can lead to a further decrease in the cell area, delay time, energy consumption, etc (Figure 4c,d).^{[ 100 ]} Despite some of the highlighted works being mainly lithography‐based, the same concept applies to printed electronics as well and the inspiration highlights the importance of system‐technology co‐optimization in printed/hybrid electronics.

Figure 4.

The layouts for 3D integrated circuits that could potentially reduce the area usage. a) the 3D stacked n‐ and p‐type transistor with a shared gate. b) The layout (front and side view) of a 3D 2‐input NAND gate using the shared gate design. c) The layout (front and side view) of the 3D inverter using the shared gate design. d) The layout (front and side view) of 3D 2‐input NOR using the shared gate design. a) Reproduced with permission.^{[ 99 ]} Copyright 2016, WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim. b–d) are re‐drawn based on the figure from the same paper. e) The layout of backgated SRAM using 1 layer, 2 layers, and 3 layers design. f) The layout of SRAM uses 1 layer, 2 layers, and 3 layers design. e,f) Adapted with permission^{[ 100 ]} Copyright 2020, IEEE.

With increasing device density, several potential concerns may arise. For example, the stable interconnects between various layers of 3D architecture and the strategies to effectively dissipate the heat generated during operation become critical due to the increased thermal resistance and device density. A few worthwhile studies have been reported to analyze the thermal management plan for the 3D integrated system based on 2D materials and this could be extended to other materials too.^{[ 101 ]} As shown in Figure 5a, the effect of the vertical heat flow has been studied with densely stacked FETs based on MoS₂ and h‐BN, interconnected by doped graphene nanoribbons. The in‐plane and out‐of‐plane heat transfer can be considered to follow in a resistive network fashion, like the case of electrical current distribution. Increasing the interlayer thickness could also lead to an increase in the operation temperature. Within the active electronic device (i.e., FET), the hot spots tend to be located at the drain‐channel contact. The heat dissipation path is determined by both the in‐plane and out‐of‐plane thermal resistance (Figure 5b): at a low inter‐layer dielectric thickness, the heat dissipation is dominated by the out‐of‐plane path; with an inter‐layer dielectric thickness greater than a critical value, the heat is preferentially transferred along the device (Figure 5c).

Figure 5.

Simulation for 3D integrated electronics based on 2D materials. a) The simulated heat dissipation network. b) The heat transfer in the FET structure. c) The relationship between thermal conductance and IDL. d) The electrical screening uses graphene as a back gate or screening layer. e) The simplified 1D noise coupling model uses multi‐layer graphene as the screening layer. f) The simulated potential variation with respect to the ILD thickness. g) Schematic showing the screening of the high‐frequency electric field using graphene. h) The relationship between graphene conductivity and frequency and network parameter g21 and frequency, respectively. Reproduced with permission.^{[ 101a ]} Open access.

The inter‐tier coupling induced electrical noise is another aspect to consider in the design of layered structures and a proper simulation framework needs to be developed for 3D integration of printed electronics. So far, few works only have focused on this aspect. Examples can again come from relevant studies in existing fields such as nanoelectronics. For instance, a system that uses graphene as a back gate/screening layer and TMDs as semiconductor materials (Figure 5d,e).^{[ 101a ]} As in the case of DC operation, the use of multilayer graphene as the screening layer could significantly reduce the 2D channel potential variation, thus contributing to the reliability of the 3D stacked electronic system (Figure 5f). For the case of high‐frequency applications, the inter‐tier screening is achieved via interface reflection and absorption (Figure 5g).^{[ 101b ]} Network parameter G₂₁ has been used to quantify the inter‐tier coupling strength (i.e., through voltage multiplication factor), with larger value indicating a stronger influence between tiers. In this regard, doping the graphene screening layer could significantly promote the screening performance. With a fermi level of ≈0.4 eV, the screening performance of graphene is like that of the copper (Figure 5h). This study provides insight into thermal and noise management in 3D‐integrated electronics based on 2D materials. More studies are needed for printed electronics based on other material systems such as Si nanostructures‐based printed circuits with 3D architectures, or the electronic systems developed using multiple materials in different layers.

4.2. Process Efficacy & Resource Efficiency

One critical bottleneck in the manufacture of monolithic 3D electronic systems is the conflict between the thermal budget during fabrication (e.g., back‐end‐of‐line metal interconnects will be damaged at high temperatures) and the requirement for forming the ohmic metal‐semiconductor contact that is usually carried out at the high temperature. For these reasons, the early works on 1D material‐based monolithic 3D systems are mainly focused on Ge/Si (core/shell) NW heterostructures (Figure 6a):^{[ 102 ]} The processing temperature requirement for this type of device is significantly lower because no additional doping is required. On the other hand, the standard Si‐based MOSFETs require thermal annealing at a high temperature (from ≈450 °C onward) for doping activation and junction formation, etc. The elimination of high‐temperature sintering is because the band structure of the Ge/Si (core/shell) nanowire allows the formation of 1D hole gas in the Ge core region and thus the ohmic type of contact could be realized without any doping, at the cost of a small tunneling barrier. This allows the fabrication of transistors at low temperatures and the layer‐by‐layer 3D integration by contact printing, as shown in Figure 6a.

Figure 6.

The status of 3D integrated electronics using 1D materials. a) The monolithic 3D integration realized by contact printed NWs in a layer‐by‐layer manner. Reproduced with permission.^{[ 102a ]} Copyright 2007, American Chemical Society. b) The achievement of X‐3D using quasi‐1D materials using the spin‐coating method. This is potentially printable using techniques such as inkjet printing and bar coating. Reproduced with permission.^{[ 103 ]} Copyright 2019, IEEE. c) The scheme and circuit diagram of all printed, CNT digital inverters. d) The electrical response of all printed CNT digital inverters and its use as gas sensors. c, d) Reproduced with permission.^{[ 104 ]} Copyright 2022, The Royal Society of Chemistry.

The conflict between maintaining a low thermal budget in 3D integration and achieving a good contact quality could be resolved for 1D materials using strategies such as “X3D”.^{[ 103 ]} The developed method, as shown in Figure 6b, includes a) decoupling the synthesis (and doping) process on foreign donor substrates and releasing them in solution–this avoids carrying out the high‐temperature synthesis steps at the site of integration; b) the uniform doping of nanostructures allows them to be placed at arbitrary locations–no additional doping for source and drain regions are required; c) the ultra‐thin body thickness of quasi 1D materials is ideally fitted for junction less transistor concept–thanks to the strong electrostatic field effect control. In this way, the formation of the source and drain regions does not require additional sintering steps, thus making the layer‐by‐layer integration shown in Figure 6b possible.

While the past efforts in 1D material applications have focused on hybrid methods involving both printing and conventional techniques such as lithography and deposition, recent works have also demonstrated the 3D integration of 1D material‐based electronics using printing alone. However, this usually comes at the cost of non‐ideal metal‐semiconductor contact because contact region doping and sintering are not employed. One example is shown in Figure 6c where two p‐type CNT FETs are employed to build an inverter, with one at the lower level acting as the drive transistor and the other at the upper level acting as the load resistor. The exposure of the upper‐level load resistor will thus lead to a switching voltage shift of the inverter as shown in Figure 6d. However, there remains a significant disparity in performance metrics such as field‐effect mobility, subthreshold slope, contact resistance, and device‐to‐device uniformity between state‐of‐the‐art 1D material‐based field‐effect transistors (FETs) developed using conventional approaches (proper doping at the contact region) and those fabricated via fully printed routes and more efforts are needed to bridge this gap in all printed 1D material‐based electronics.

Comparatively, the integration of 2D material‐based devices in the 3D stack is potentially more straightforward because high‐quality contacts can be achieved at lower temperatures (e.g., <300 °C for graphene, MoS₂, MoSe₂),^{[ 105 ]} effectively bypassing many of the thermal budget related constraints discussed above for 3D integration.^{[ 106 ]} In lithography‐based processes, monolithic 3D ICs using transition metal dichalcogenides (TMDs) have been realized at the 14 nm technology node,^{[ 99 ]} highlighting the potential of 2D materials for 3D integration within traditional CMOS‐compatible technology frameworks.

On the other hand, layer‐by‐layer assembly using transfer printing has been extensively researched in the field of 2D material‐based devices.^{[ 106 ]} While at first glance it appears to be less reliable than traditional deposition‐based techniques, the pick‐and‐place strategy offers an additional dimension–interlayer coupling–for fine‐tuning device response.^{[ 107 ]} Compared to deposition‐based fabrication techniques, the van der Waals (vdW) nature, inherent in transfer printing, offers unrivaled potential for achieving ultra‐clean contact interfaces.^{[ 108 ]} Coupled with advances in vdW gap control,^{[ 107a ]} all 2D material devices based on transfer printing hold more promise for scalability than previously thought.

The transfer printing approach is substantially more resource‐efficient than traditional fabrication techniques, particularly for devices using graphene (or other semi‐metals) as source and drain contacts. The elimination of CRMs, in this case, makes these printed contacts more sustainable. From a device physics perspective, the semi‐metallic properties of graphene open the channel to fine‐tune the Fermi level via the local gate voltage. This provides a unique advantage as there is the possibility to tune the metal‐semiconductor junctions. In addition to graphene, vdW transfer of evaporated metal films (e.g., Au) has also been investigated for forming source and drain contacts, offering intrinsic contact interfaces free of chemical disorder and Fermi‐level pinning. Both methods are promising for vertical device integration. For example, vertical integration of transistors up to three layers has been successfully demonstrated using graphene as the contact and h‐BN as the dielectric material (Figure 7a).^{[ 109 ]} As recently demonstrated, a similar strategy using Au as the contact is also feasible (Figure 7b).^{[ 110 ]} As we move toward large‐scale integration, one of the main challenges lies in tuning the threshold voltage, as well as achieving performance uniformity, for specific circuit designs (Figure 7c).^{[ 111 ]}

Figure 7.

The possible strategies to realize 3D integrated electronics using 2D materials. a) The monolithic 3D integration of 2D TMDs using transfer printing by employing graphene as contacts. Adapted with permission.^{[ 109 ]} Open access. b) The monolithic 3D integration of 2D TMDs using transfer printing by employing transferred Au as contacts. c) The demonstration of large‐scale electronics manufacturing using transfer printing. Adapted with permission.^{[ 111 ]} Copyright 2023, Springer Nature.

Thin‐film transistor (TFT), particularly one with organic semiconductors as the active materials, is another kind of device widely explored in printed electronics. The first demonstration of the vertically integrated organic TFTs was reported in 2008, when the stack of bottom‐gated, top‐contacted organic FETs, based on pentacene, were realized.^{[ 33 ]} The prototype, though, was fabricated by conventional micro‐fabrication methods including lithography and metal deposition. A passivation layer was needed to protect the devices on the first layer from potential damage from the later micro‐fabrication processes. Till now, there have been many such demonstrations in the system of OFET, fabricated using various printing technologies.^{[ 98} , ^{112 ]} For instance, stacked complementary OFETs realized using inkjet printing can achieve a 100% device yield over a scale of ≈100 devices (Figure 8a,b), on/off ratio≈10⁵, ohmic‐type of contact and stable performance (Figure 8c,d). Vertical integration allows a more compact design for various circuits including inverters, flip‐flops, and more (Figure 8e–h).^{[ 113 ]} Since the organic TFT is known for its restricted thermal budget compared to the inorganic TFTs, their vertical integration is appealing as it naturally bypasses many of the fabrication constraints.

Figure 8.

3D integration of thin‐film transistors. a) The scheme shows the 3D integration of p‐ and n‐ types of organic transistors b) The optical microscopy images showing the 3D integration of organic transistors. c,d) The transfer and output characteristics of the 3D integrated organic transistors. a–d) are adapted from ref. [98a] with permission. Copyright 2016, American Chemical Society. e) The scheme shows the 3D stack of single‐gate transistors and double‐gate transistors. f) The photograph and response of the single gate and double gate ring oscillators. e,f) Reproduced with permission.^{[ 113a ]} Copyright 2019, IEEE. g) The photograph shows the peeling of flexible electronics from its carrier substrate. h) The microscopy image shows the inkjet‐printed transistors. g,h) Reproduced with permission.^{[ 113b ]} Open access.

On the other hand, inorganic semiconductor thin films, such as metal oxides and Si nanomembrane, are another popular candidate for thin film transistors. For metal oxide, both physical vapor deposition and solution‐based methods have been developed for the fabrication of the thin film. Indeed, PVD‐based metal oxide TFTs present higher performance in general, the studies carried out in the past two decades on solution‐based TFTs, particularly those based on sol‐gel methods, have shown good promise in large‐scale fabrication on flexible substrates with good device uniformity and carrier mobility.^{[ 114 ]} Some of the printed metal oxide TFTs have been found to exhibit higher carrier mobility (i.e., ≈20 cm² V⁻¹s⁻¹)^{[ 114} , ^{115 ]} than amorphous silicon (i.e., ≈1 and 0.003 cm² V⁻¹s⁻¹ for electrons and holes, respectively),^{[ 116 ]} and have been widely used for applications such as driving backend for OLEDs, digital computing, etc. However, while the n‐type candidate such as IGZO is rather established, there is a lack of a reliable and mature candidate for p‐type devices. To this end, heterogeneous integration between n‐type metal oxide and p‐type technologies (e.g., amorphous Si, carbon nanotubes, organic semiconductors, 2D materials) for a CMOS layout, either in a 2D or 3D manner, is drawing increasing attention.^{[ 117 ]} Another noteworthy candidate is the Si nanomembrane that can be fabricated using SOI wafers using the top‐down method and then transferred at designated substrates.^{[ 41b ]} Benefiting from the mature Si CMOS technology, crystalline Si nanomembrane‐based devices do not need to face the problem of lacking a p‐type candidate: The advantages of these devices are their high carrier mobility (e.g., carrier mobility reaching 600 cm² V⁻¹s⁻¹).^{[ 37a ]} However, since the top‐down fabrication of the thin film still involves some conventional microfabrication steps, they are not fully printed and have a disadvantage in resource efficiency.

4.3. Strategies for Vertical Interconnection

The electrical connections between devices from different layers are another indispensable aspect of 3D integration. In conventional Si CMOS, this is achieved by strategies such as Si vias (TSVs), wire bonding, flip chip technology, etc. However, these technologies pose restrictions and are incompatible with some of the typical materials/substrates used in printed electronics. For example, standard chip‐to‐chip 3D bonding can be realized at a temperature of ≈300 °C,^{[ 118 ]} which many polymeric substrates and organic semiconductors cannot withstand. Printed electronics is also often associated with flexible and stretchable electronics. Therefore, the interconnects, on many occasions, may be subjected to mechanical deformation, particularly when they are used in foil‐to‐foil integration. This calls for the development of new solutions for vertical interconnect for printed 3D electronics.

One effort to comply with the temperature restriction is the recently demonstrated water vapor plasma–assisted bonding. By taking advantage of the plasma‐generated hydroxyl groups, a strong and stable bonding interface can be formed. This could provide an effective approach to bond the Au‐to‐Au surface at room temperature and ambient pressure (Figure 9a).^{[ 119 ]} The bonded interconnects are shown to provide excellent conductivity (i.e., an interface resistance ≈0.07 ohms) and stability upon various conditions (<1% conductance change after 10,000 bending cycles with a 2.5‐mm bending radius), resulting in a reliable solution for printed flexible and stretchable electronics.

Figure 9.

Printing techniques for boding in 3D integrated electronics, especially on the soft substrate. a) Au─Au bonding on the flexible substrate. Reproduced with permission.^{[ 119 ]} Open access. b) Bonding by printing. Reproduced with permission.^{[ 120a ]} Open access.

Another effort worth mentioning is bonding by printing. The drop‐on‐demand fabrication allows the resource‐efficient, point‐to‐point connection, compared to the traditional method like TSVs where steps like seed layer deposition, electroplating, and chemical mechanical polishing for planarization are employed. However, the height difference requires the printed conductive inks to overcome the high vertical steps to form 3D interconnects. To this end, inks with high viscosity are preferred. For example, printed Ag inks of high viscosity have been employed to realize interconnects between the thinned chip and the flexible holding substrate (Figure 9b).^{[ 120 ]} The high viscosity of the ink enables the effective coverage of the topological steps between different surfaces. This provides another effective manner to realize 3D integration that is compatible with flexible and stretchable electronics. In another study high resolution printing is used for obtaining vertical interconnection accesses (VIAs). This approach for vertical interconnect structures used two different types of high‐resolution printers (electrohydrodynamic and extrusion‐based direct‐ink writing) for the development of high‐density 3D integrated flexible hybrid electronic (FHE) systems. Comprehensive studies comparing and benchmarking: i) the speed and throughput of the high‐resolution printers, ii) the electrical performance of vertically interconnected transistors in ultra‐thin chips, and iii) the performance stability of heterogenous systems under mechanical bending, are presented.

Printed hybrid electronics often involve the use of chemically sensitive materials that are not compatible with photolithography. The interconnect formation between different layers, on certain occasions, requires the local etching of the insulating materials, i.e., the via‐hole process. This conflict mandates the development of a via‐hole‐less strategy for 3D interconnects. To this end, selective dielectric formation using shadow masks has been demonstrated to achieve multilevel metal interconnects.^{[ 121 ]} This technology enables the highly stacked organic electronics with transistors on five different layers. Another possible strategy to address the interconnects problem is to use laser drilling to create the via hole in the dielectric locally,^{[ 98} , ^{122 ]} but this may lead to extra heat on the substrate. In this regard, the layout that arranges the active device and interconnects should be carefully planned. On the other hand, optical interconnects receive more attention in flexible electronics owing to the benefit of less power consumption, voltage isolation, etc. Recently, printed optical interconnects have been explored,^{[ 123 ]} which could potentially be used for data communication between components in different planes.

4.4. Density, Functionality and Yield

The main motivation for implementing a 3D layout is to augment the device density, and consequently enhance the functionality of the whole system. For printed electronics, vertical integration seems to be more important as its device density is still several orders of magnitude lower than the Si CMOS. The vertical integration allows for the areal density increase without tackling the basic fabrication challenges in the physical scaling of the devices. Table 2 summarizes the representative work in printed and non‐printed electronics, on both rigid and soft platforms with their device density and performance.

Table 2.

Comparison of device density of 2D & 3D electronics based on printing, hybrid, or nonprinting techniques.

Materials	Device architecture	Device density	Performance	Fabrication method	Thermal budget	Form factor	Applications	Refs.
Ge/Si NWs	3D	≈54 transistors mm−2	Transconductance≈1mS (p‐type)	hybrid	low temperature (lithography range)	flexible	digital circuits	[102a]
CNTs	3D	≈10 transistors mm−2	15 and 9 cm2 V−1s−1 (n and p‐type)	lithography	low temperature (lithography range)	flexible	digital circuits, etc	[102c]
2D materials (WSe2)	3D	sub‐0.01 µm2 memory cells	230 cm2 V−1s−1	hybrid	< 400 °C	rigid	Selector for memory	[124]
2D materials (WSe2 and MoS2)	3D	NA	38 and 238 cm2 V−1s−1 (n and p‐type)	hybrid	low temperature (lithography range)	rigid	digital circuits, etc	[99]
2D materials/III‐V compound semiconductor (MoS2 & GaN)	3D	≈2500 transistors mm−2	54 cm2 V−1s−1 (n‐type)	hybrid	low temperature	rigid	active matrix‐driven LED	[125]
Organic Semiconductors	2D	≈3.47 transistors mm−2	0.82 cm2 V−1s−1 (p‐type)	hybrid	<200 °C	stretchable	active matrix, digital circuits, etc	[126]
Organic Semiconductors	3D	≈0.6 transistors mm−2	0.086 and 0.7 cm2 V−1s−1 (n and p‐type)	inkjet printing	≈120 °C	flexible	digital circuits, etc	[112b]
Organic Semiconductors	3D	NA	NA	deposition based	≈200 °C	flexible	digital circuits, etc	[127]
2D materials (MoS2)	2D	7.2 transistors mm−2	SS ≈153 ± 45 mV Dec−1	hybrid	≈160 °C	rigid	digital circuits	[111]
Organic Semiconductors	3D	0.006 transistors mm−2	0.21 and 0.34 cm2 V−1s−1 (n and p‐type)	inkjet printing	≈120 °C	flexible	digital circuits	[113b]
Organic Semiconductors	2D	1000 transistors mm−2	20 cm2 V−1s−1	lithography and etching	<200 °C	stretchable	Digital circuits	[35]
Metal oxide	2D	≈950 transistors mm−2	10‐40 cm2 V−1s−1	lithography and PVD	<250 °C	flexible	Microprocessor	[128]
Metal oxide	2D	NA	≈230 cm2 V−1s−1	hybrid	<250 °C	rigid	Digital circuits	[129]
Si nanomembrane	2D	NA	≈400 cm2 V−1s−1	hybrid	Up to 1050 °C but decoupled with the target substrate	stretchable	Digital circuits	[130]
Si nanomembrane	2D		≈600 cm2 V−1s−1	hybrid	Up to 1050 °C but decoupled with the target substrate	flexible	NA	[37a]

Some of the materials listed in Table 2 are promising for high‐performance electronics. Nevertheless, the currently achievable device density is still far from that of the Si CMOS. Because of this, the application scenarios demonstrated are still limited at the moment. A popular example is the control circuitry for an active sensing matrix that prevents crosstalk between the neighboring pixels, with several demonstrations made using various materials.^{[ 126} , ^{131 ]} In the meantime, researchers are also actively pursuing using printed electronics for medium‐ to large‐scale digital logic and analog circuits. Current demonstrations include ring oscillators,^{[ 132 ]} amplifiers,^{[ 133 ]} filters,^{[ 134 ]} spiking neuron circuits,^{[ 135 ]} and more. Despite the advances reviewed so far, the current bottleneck still lies in achieving good uniformity over a large‐scale of devices with a high yield.^{[ 136 ]} The 3D integration could magnify this issue as the combination of the yield of each layer could be significantly lower. In this regard, the short‐term strategy may be the hybrid integration of printing and non‐printing technologies or a hybrid fabrication method that blends the printing and non‐printing techniques. This includes, for example, the use of printing technology to realize the channel region while the source/drain contacts and dielectrics are achieved by conventional microfabrication methods such as photolithography and metallization.^{[ 137 ]}

Following the above discussion, hybrid integration between the thinned Si chips and the printed electronics (on flexible substrates) is particularly noteworthy. The Si chips provide a much mature technology route to realize some complicated electronic systems while the thinned chip may only provide limited flexibility. By contrast, the printed electronics on the flexible substrate can be far more flexible while its functionality may not be as good as the Si chips–at least with current state‐of‐the‐art printing tools. They hybrid integration of both, if arranged properly, could be an interesting and viable way forward in the near‐ to mid‐term. In this regard, the hybrid integration of the thinned chips and printed electronics can be complementary to each other both in terms of functionalities and mechanical flexibilities.^{[ 138 ]} Inspirations can be taken from examples following non‐printing manufacturing methods as well. For example, the hybrid memristor/CMOS system has been demonstrated by vertical integration of the two dies, showing advantages in terms of reduced interconnect length and power consumption.^{[ 139 ]} Layer‐by‐layer fabrication of computing and memory layer leads to a monolithic 3D integration.^{[ 140 ]} With these guiding examples, it is expected that similar demonstrations will arise in printed electronics as well in the near‐ to mid‐future.

5. Novel Functionalities in 3D Hybrid to Fully Printed Electronics

Printed electronics are particularly interesting as they enable new ways of using electronics developed on various novel substrates. The 3D integration of printed electronics will further open new avenues for functionalities that are not possible to be realized by conventional or printed electronics alone in a 2D manner.

5.1. 3D Integrated, Stretchable, Electronic System

Currently, stretchable electronics are realized primarily following two strategies: 1) realizing the electronic device with materials of low elastic modulus;^{[ 40 ]} 2) realizing a stretchable system with structure designs at different levels (e.g., stretchable interconnects).^{[ 141 ]} The device density achieved by both strategies, as of today, is limited, which hinders the complex stretchable system implementation. To this end, a 3D integration strategy could become an effective manner to tackle such a problem in stretchable electronics, particularly with the system in package type configuration. Although the concept of stretchable electronics has been proposed for more than a decade, the work mainly focuses on in‐plane stretching, both in a uniaxial and biaxial manner. In this regard, realizing a 3D integrated system with stretchability over the three dimensions itself is meaningful. Recently, demonstrations have been made using different components such as sensors, amplifiers, and Bluetooth chips distributed in PDMS elastomer of various layers to increase the overall stretchability of the system in all directions (Figure 10a,b).^{[ 142 ]} The devices in each layer are connected through vertical interconnect vias (VIA) in the elastomer. Such novel designs could accommodate the need for a complex electronic layout while maintaining the stretchability of the system in a 3D manner, providing more versatility than the system in 2D. Efforts have also been dedicated to increasing the function density of the system by taking advantage of stacked multilayer network materials to accommodate the stretchable system. For example, with the novel design shown in Figure 10c,d, the demonstrated system offers a function density of up to ≈110%.^{[ 143 ]} Indeed, the demonstrated works employed off‐the‐shelf components for the system in package realization, looking forward, with the advances in printed electronics, demonstration of complex electronic systems with highly dense, fully printed devices and circuits, with high mechanical freedom is expected.

Figure 10.

The 3D integrated stretchable electronics. a) The 3D integrated electronic system on the 3D PDMS scaffold. b) The twisting and poking of the realized 3D stretchable system. a, b) Reproduced with permission.^{[ 142 ]} Copyright 2018, Springer Nature. c) The methodology utilizes the porous substrate to realize highly dense, stretchable 3D integrated electronics. d) The 3D arrangement and simulation result of the 3D stretchable system. c, d) Adapted with permission.^{[ 143 ]} Open access.

5.2. 3D Stacked, Transient Electronics

Transient electronics is another emerging field that aims to realize electronic devices that can disintegrate or physically disappear under certain conditions in a controllable manner. Contrary to the conventional electronics that aim to work over the long term, if not indefinitely, transient electronics are designed only to serve temporarily.^{[ 29} , ^{144 ]} Once integrated in 3D, this new form of electronics can not only lead to a device density increase but also enable functionality transformation in a controlled manner upon degradation. One demonstration made recently shows an AND gate realized by connecting a NAND gate in the first tier and an inverter in the second tier.^{[ 145 ]} The complete electronic system is biodegradable, but such a system can be dissolved in a layer‐by‐layer manner (Figure 11 ). Therefore, there is a certain period when the inverter on the 2nd layer has been fully dissolved but the device on the first tier remains intact and functional, leading to a transformation of the system functionality (e.g., from NAND gate to AND gate). This demonstration opens a new avenue for transient electronics in which the functionality of the electronic devices can vary in a pre‐programmable manner. While such features are attractive, the post‐degradation analysis of transient electronics, to understand the nature of by‐produces (useful or not), is an area that needs attention too.

Figure 11.

The 3D integrated transient electronics with controlled functionality upon degradation for both analog and digital design. Adapted with permission.^{[ 145 ]} Copyright 2018, WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim.

6. Conclusion

In summary, the 3D integration is knocking at the doorsteps of printed electronics and there is already some indication of the transition from the historical development of traditional Si CMOS. In this way, the fundamental limitation of device density in printed electronics could potentially be alleviated. This opens a promising approach for printed electronics to evolve from small‐scale/medium‐scale integration to large‐scale integration (LSI), with much more complicated electronic design, layout, and functionality. In addition, the integration of printed electronics vertically also enables various novel architectures (e.g. out‐of‐plane devices) and functionalities such as 3D stretchability and transient electronics with programmed functionality transformation, which are difficult to realize with traditional electronics or printed electronics confined in a 2D plane alone. However, the progress of printed electronics is still largely constrained by technological limitations such as the lack of sub‐micron printed features and other fundamental challenges related to device engineering and performance control over a large area. In this aspect, the development of the 3D integration technique alone is not enough. While the hybrid integration of printed electronics and conventional electronics can be an interesting short‐term solution, fully printed electronics of high performance on various platforms can offer more applicability and opportunities in the field of large‐area electronics. Both strategies are being actively researched and their convergence could open new opportunities for the printed electronics industry. In this regard, the 3D integration techniques, reviewed in this article, will be a promising component to accelerate the development of both, toward large‐area, low‐cost green electronic systems.

Conflict of Interest

The authors declare no conflict of interest.

Biographies

Fengyuan Liu obtained his Bachelor's and Master's degrees from Nanjing University in 2012 and 2015, respectively, and received his Ph.D. in Engineering from the University of Glasgow in 2020. He is currently a Marie Curie Global Postdoctoral Fellow at Fondazione Bruno Kessler in Trento, Italy, and Northeastern University in the United States, where he leads the project: “Neuro‐encoded Electronic Skin (NEUCODES).” Additionally, he serves as the researcher Co‐I on the UK Engineering and Physical Sciences Research Council (EPSRC)‐funded project “Green Optimized Printed Integrated Circuits (GEOPIC).” His research interests include electronic skin, robotic tactile sensing, and printed and flexible electronics.

Adamos Christou is a post‐doctoral researcher and member of the Bendable Electronics and Sustainable Technologies (BEST) Group, based at Northeastern University in Boston, MA. He received a PhD degree in Electronics and Electrical Engineering from the University of Glasgow, UK in 2024 and a B.Eng. (Hons.) degree in Mechatronics Engineering from the University of Glasgow in 2018.

Abhishek Singh Dahiya is a post‐doctoral researcher and member of the Bendable Electronics and Sustainable Technologies (BEST) Group, based at Northeastern University in Boston, MA. He received a Ph.D. degree from the GREMAN Laboratory, Université François Rabelais de Tours, France. His current research interests include nanomaterials synthesis, nanofabrication, energy harvesting, and printed/flexible electronics.

Ravinder Dahiya, Fellow of IEEE and the Royal Society of Edinburgh, is a Professor in the ECE Department at Northeastern University, USA, where he leads the Bendable Electronics and Sustainable Technologies (BEST) group. His multidisciplinary research includes flexible and printed electronics, electronic skin, and their applications in robotics, wearables, etc. He has authored more than 500 publications, submitted/granted patents and disclosures, and led many international projects. He is serving on the Board of Directors of IEEE and is the Past President of the IEEE Sensors Council. He is the Editor‐in‐Chief of npj Flexible Electronics and was the Founding Editor‐in‐Chief of IEEE Journal on Flexible Electronics.

Liu F., Christou A., Dahiya A. S., Dahiya R., From Printed Devices to Vertically Stacked, 3D Flexible Hybrid Systems. Adv. Mater. 2025, 37, 2411151. 10.1002/adma.202411151