Table 3.

Architecture of the detail branch and semantic branch of the BiSeNeXt network.

Stage	Detail branch			Semantic branch					Output size
	opr	c	s	opr	c	e	s	r
S1	DFEB	32	1	Stem	16	–	4	1	512×512
	EAMA	32	1						512×512
	DFEB	32	2						256×256
S2	DFEB	64	1						256×256
	EAMA	64	1						256×256
	DFEB	64	2						128×128
S3	DFEB	128	1						128×128
	EAMA	128	1						128×128
	DFEB	128	2						64×64
S4	DFEB	128	1	GE	32	6	2	1	64×64
	EAMA	128	1	GE	32	6	1	1	64×64
	DFEB	128	1						64×64
S5				GE	64	6	2	1	32×32
				GE	64	6	1	1	32×32
S6				GE	128	6	2	1	16×16
				GE	128	6	1	3	16×16
				CE	128	–	1	1	16×16