Fig. 2. Highly symmetric and uniform CMOS building blocks.
(A) Band diagrams of the Pd contact PMOS and NMOS devices in the “on” state. (B) Transfer curves of the PMOS (blue) and NMOS (red) devices, with |Vds| varying from 0.2 to 2 V in steps of 0.2 V. (C) Output curves of the PMOS (blue) and NMOS (red) devices, with |Vgs| varying from 0 to 2 V in steps of 0.2 V. (D) Transfer curves of 150 PMOS (left) and 150 NMOS (right) devices, with Vds set at −2 and 2 V, respectively. (E) Statistical analysis of the Ion, Ioff, SS, and Vth for the PMOS (blue) and NMOS (red) devices shown in (D).