Table 1.

Comparison of previous D-latch and D-flip-flop designs and their weaknesses.

Reference	Design	Number of cells	Area (um²)	Delay (clock cycles)	Key weaknesses
12	Simple D-latch	48	0.05	1	High area and cost, making it economically unfeasible for practical applications.
17	D-latch for PFD design	28	0.03	0.5	Complex design with multiple gates, still not optimal in terms of scalability and simplicity.
10	D-latch (simple, set/reset)	30	0.02	1	High number of cells for set/reset functionality, resulting in larger area compared to other designs.
22	D-latch (simple, set/reset)	21	0.01	1.25	Despite reducing the cell count, the delay of 1.25 clock cycles limits its performance in high-speed apps.
24	Optimized D-latch	36	0.03	0.75	Higher delay compared to other optimized designs, not ideal for applications requiring low delay.
20	D-flip-flop (rising edge)	84	0.11	2.5	Excessive cell usage, high delay, inefficient for practical use due to high complexity and cost.
10	D-flip-flop (rising edge, reset)	53	0.04	2.25	High delay and excessive use of cells make it unsuitable for cost-effective, large-scale applications.
22	D-flip-flop (reset)	41	0.03	1	Large number of cells and area, not ideal for future implementations requiring small area and low cost.