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. 2025 Aug 22;15:30959. doi: 10.1038/s41598-025-15949-y

Table 7.

Energy dissipation of proposed D-latches, D Flip-Flops, and 4-bit shift register.

Average switching energy dissipation Average leakage energy dissipation
Inline graphic Inline graphic Inline graphic Inline graphic Inline graphic Inline graphic
Figure 6 Inline graphic 0.0050 0.0061 0.021 0.0115 0.0041
Figure 9 Inline graphic 0.0021 0.0030 0.0437 0.0254 0.009
Figure 10 Inline graphic 0.063 0.076 0.1245 0.0564 0.0123