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. 2025 Oct 13;15:35661. doi: 10.1038/s41598-025-19530-5

Table 3.

Switching scheme of proposed 25-level inverter.

State S1S2S3S4K1K2T1T2T3T4 Vo
1

1,010,001,000

0101000001

 0
2 0001100001 1Vdc
3 1,001,000,001 2Vdc
4 0100011000 3Vdc
5 0000111000 4Vdc
6 1,000,011,000 5Vdc
7 0000110010 6Vdc
8 1,000,010,010 7Vdc
9 0101001000 8Vdc
10 0001101000 9Vdc
11 1,001,001,000 10Vdc
12 0001100010 11Vdc
13 1,001,000,010 12Vdc
14 0000101000 −1Vdc
15 0101000100 −2Vdc
16 1,000,010,001 −3Vdc
17 0000110001 −4Vdc
18 0100010001 −5Vdc
19 0000110100 −6Vdc
20 0100010100 −7Vdc
21 1,010,000,001 −8Vdc
22 0010100001 −9Vdc
23 0110000001 −10Vdc
24 0010100100 −11Vdc
25 0110000100 −12Vdc