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. 2025 Dec 10;17:702. doi: 10.1038/s41467-025-67309-z

Fig. 2. Experimental demonstration of the in-memory probabilistic computing (p-computing) system and the artificial probabilistic bit (p-bit).

Fig. 2

a Schematic of the compute-in-memory (CIM) hardware mapping under the discrete Hopfield Neural Network (DHNN) architecture, in which interconnection values are encoded using pairs of RRAM cells. A p-bit with tunable stochasticity is activated by different numbers of cells in the bias region. b 1T1R structure of the DHNN hardware, which needs to be used in conjunction with subsequent Gaussian random number generator (GRNG) and comparator circuits. c Photograph of the p-computing chip integrating the 1T1R RRAM array with the 180-nm CMOS technology. d Characteristics of switching curves of the standalone RRAM cell. e Experimentally measured cumulated bit line (BL) current, namely the multiply-accumulate (MAC) output by activating different numbers of word lines (WLs) at different WL voltages. f Bias current distributions controlled by the sigma value of the GRNG at standard deviation σ = 0.5, 1, and 2. g A series of sigmoidal probability curves of the artificial tunable p-bit (probability of output being 1) under different sigma values ranging from 0 to 2. h Time snapshots of the output states for three different inputs (MAC = +4, 0, and −4, respectively) observed experimentally (solid blue line) and by simulation (solid red line) at σ = 2.