Device to Circuit Co‐Design Utilizing High‐Performance PEALD Indium‐Gallium‐Zinc Oxide Thin‐Film Transistor Enabling Technology Node Scaling in Monolithic 3D Systems

Abstract

The development of oxide semiconductor devices for monolithic 3D (M3D) integration has largely remained at the device level, limiting progress toward large‐scale applications. To advance this technology, evaluation from device to circuit level—akin to CMOS—is essential. This work presents a comprehensive study of M3D‐compatible technology using indium‐gallium‐zinc oxide (IGZO) thin‐film transistors (TFTs) fabricated via plasma‐enhanced atomic layer deposition (PEALD). The investigation spans material characterization, device performance, technology computer‐aided design (TCAD) Modeling, circuit design, and scaling projections. At device level, comprehensive material and electrical characterizations elucidate intrinsic property interdependencies in IGZO TFTs, which exhibit a field‐effect mobility (µ_FE ) up to 116.35 cm² V⁻¹·s⁻¹, high reliability (△V_TH < 0.15 V), and low variation (△µ_FE < 2%). These results enable accurate TCAD models for system‐level co‐design of unipolar TFT circuits, including pseudo‐CMOS inverters, 5‐stage ring oscillators (ROs), and static random‐access memory (SRAM) cells, all exhibiting robust functionality. For future technology scaling, projections to the 22 nm node show RO frequencies up to 240 MHz and SRAM switching times as low as 0.78 ns, with strong dynamic and noise characteristics. This work offers critical insight into circuit‐level performance of PEALD IGZO TFTs and provides valuable guidance for the implementation of oxide semiconductor‐based M3D systems.

This article presents a holistic investigation of M3D‐compatible oxide semiconductor technology using PEALD‐fabricated IGZO TFTs, spanning device‐level characterization, TCAD Modeling, circuit design, and scaled‐node projections. It demonstrates high field‐effect mobility (up to 116.35 cm² V⁻¹·s⁻¹), robust reliability (△V_TH < 0.15 V), low variation (△µ_FE < 2%), and forecasts 240 MHz ring oscillators and 0.78 ns SRAM at 22 nm.

1. Introduction

In recent years, the demand for computing power has been increasing exponentially as artificial intelligence (AI) and big data analysis applications continue to grow, further exacerbated with the emergence of advanced large language models requiring unprecedented computing power. Moore's Law, which has driven the progress of microelectronics for over fifty years, is going to face significant challenges as transistor scaling in the 2D plane is approaching its physical limit.^{[ 1} , ^{2 ]} 3D computing systems that integrate embedded logic and memory devices monolithically offer a promising solution (Figure 1a), but requires beyond‐silicon (Si) technologies to complement.^{[ 3} , ⁴ , ⁵ , ⁶ , ^{7 ]} Of the various complementary metal‐oxide‐semiconductor (CMOS) back‐end‐of‐line (BEOL) compatible low‐temperature electronic materials such as 2D transition metal chalcogenides (TMDs),^{[ 5} , ⁸ , ⁹ , ¹⁰ , ¹¹ , ^{12 ]} carbon nanotubes (CNTs)^{[ 13} , ¹⁴ , ¹⁵ , ¹⁶ , ^{17 ]} and oxide semiconductors,^{[ 7} , ¹⁸ , ¹⁹ , ²⁰ , ²¹ , ^{22 ]} oxide semiconductors are poised to be the immediate candidate for risk production due to its mature process in large‐scale manufacturing using CMOS compatible technology.^{[ 18 ]}

Figure 1.

a) The M3D illustration. b) Photo image of the fabricated sample containing the TFT, inverter, ring oscillator, and SRAM. c) Illustration of key fabrication steps of the PEALD IGZO TFTs. d) The super‐cycle numbers for 10 nm‐thick IGZO films with varied InO_x: GaO_x: ZnO sub‐cycle ratios, with the diagram of super‐cycle and InO_x sub‐cycle in inset. e) The AFM image of the IGZO channel surface. f) The TEM image of the IGZO TFT gate stack, labelled with the different layers. g) The corresponding EDS mapping of elements taken from the gate stack.

Among potential oxide semiconductors, indium‐gallium‐zinc oxide (IGZO) is undoubtedly the one that stands out the most—not for its superior performance, but for its inherent material stability, which promises reliable performance over the long run.^{[ 23} , ^{24 ]} Nonetheless, the pursuit for the co‐existence of both its performance and stability is still on‐going, driving its integration into circuit‐level implementations within M3D systems. However, the lack in concurrently achieving both acceptable performance and stability, as well as the systematic evaluation of such class of material for circuit‐level implementation suitable for M3D integration at CMOS BEOL, hinders its progress for large‐scale implementation. For instance, at the material and device levels, conventional techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) provide limited control over film quality, making it difficult to precisely modulate defects and stoichiometry for optimal device performance. Furthermore, at the circuit level, current works are far less compared to that on material or device level, with most oxide‐based circuits preliminarily focused on simple demonstrations. System‐level investigations are even scarcer, due to the absence of robust device models capturing adequate device performance variations in a particular technology node.

Hence, in this work, we experimentally addressed the above shortcomings all the way from device to circuit level, and then projected the critical circuit‐level performance to scaled technology nodes to emphasize on the feasibility in advanced integrated circuit (IC) chips (Figure 1b). At the device level, we provided in‐depth insights on plasma‐enhanced atomic layer deposited (PEALD) IGZO thin films in modulating various key materials properties that affect the resulting device performance and stability. The PEALD approach enables deposition at exceptionally low temperatures without further post‐annealing due to the plasma aided effects of precursor reactions, while simultaneously providing precise control over stoichiometry and defect modulation. Thus, an exceptional field‐effect mobility (µ_FE ) up to 116.35 cm² V⁻¹·s⁻¹, outstanding long‐term reliability, and excellent voltage‐bias stability of threshold voltage shift (ΔV_TH ) less than 0.15 V were achieved. All the device improvement mechanisms were supported via extensive material characterization—including ultraviolet (UV) absorption, Hall effect measurements, capacitance–voltage (C–V) measurements, and X‐ray photoelectron spectroscopy (XPS) analyses. To highlight our process superiority, we characterized more than 100 devices and provided statistical analyses showing the tight distribution of the device performance, followed by the development of a technology computer‐aided design (TCAD) model methodology accounting for the device behaviors in our process technology; the model's performance and robustness were evaluated through a simulation framework that accounts for process variations.

To enable unipolar TFT‐based circuit design, we simulated both pseudo‐enhancement‐load (PEL) and conventional enhancement‐load (EL) inverters using our TCAD device model and experimentally validated them, achieving excellent agreement between simulation and measurement. We then presented 5‐stage ring oscillators (ROs) design framework based on both inverter configurations with functional experimental demonstration. Considering the importance of static random‐access memory (SRAM) process and performance in current CMOS technology, we also demonstrated the design and experimental characterization of a unipolar SRAM based on our IGZO TFT process, exhibiting excellent static and dynamic characteristics, although with the use of n‐only TFTs. This hails a significant milestone as this is the first time that pseudo‐CMOS SRAM based on unipolar oxide semiconductors suitable for BEOL integration has been reported, a key evaluation required to push this technology significantly forward. Finally, to account for their implementation feasibility at advanced technology node, we provided the performance projection of the 5‐stage RO and SRAM cell down to the 22 nm node, with the RO oscillation frequency potentially reaching a high 240 MHz, and SRAM switching time down to a remarkable 0.78 ns with excellent noise margins. Our results, encompassing IGZO TFT performance optimization, device Modeling, circuit design framework, circuit demonstration and technology projection roadmap, are expected to offer valuable guidance for the future integration of IGZO TFT‐based circuitry at CMOS BEOL as Si‐based logic circuits complements.

2. Results and Discussion

2.1. Fabrication of Devices and Circuits

Key fabrication steps of the staggered, bottom‐gated PEALD IGZO TFTs are shown in Figure 1c. The bottom‐gate electrode of Ti/Pt (3.6/15 nm) was first deposited by DC sputtering. Then, a 9 nm‐thick HfO₂ used as gate dielectric was deposited via thermal ALD at 250 °C. Following, a 10 nm‐thick IGZO layer was deposited via PEALD at 200 °C using consecutive sequences of IGZO super‐cycles. Each IGZO super‐cycle consisted of a pre‐determined set of InO_x, GaO_x, and ZnO sub‐cycle (InO_x: GaO_x: ZnO = n: 1: 1, marked as IGZO_n:1:1 ), with n = 0, 0.5, 1, 3, and 5 to elucidate the effect of indium (In) concentration. IGZO layers of 10 nm thickness were deposited in all splits. Figure 1d shows the super‐cycle numbers for the IGZO films with different InO_x: GaO_x: ZnO sub‐cycle ratios, with the diagram of super‐cycle and InO_x sub‐cycle in the inset. Finally, the source/drain (S/D) electrodes of Ti/Au (20/26 nm) were deposited using DC sputtering, followed by a lift‐off process. The fabricated TFTs have a channel width (W_CH ) of 10 µm and channel length (L_CH ) of 5 µm, with optical image shown in Figure S1 (Supporting Information). Details of the fabrication process parameters are provided in the “Experimental Section”.

Figure 1e shows the atomic force microscope (AFM) image of the IGZO channel surface, with a small root mean square roughness (R_q ) of 0.465 nm, confirming the high quality of the deposited films. Figure 1f exhibits the transmission electron microscope (TEM) image of the TFT gate stack with clear interfaces between the different layers, with the energy dispersive spectroscopy (EDS) mapping of elements in the gate stack shown in Figure 1g. The grazing incidence X‐ray diffraction (GI‐XRD) patterns exhibit faint and broad peaks at ≈32° with no sharp peaks, confirming the amorphous nature of all the deposited IGZO films,^{[ 25} , ²⁶ , ^{27 ]} as shown in Figure S2 (Supporting Information).

2.2. IGZO TFT Characterizations

Figure 2a shows the cation atomic percentages in the prepared IGZO films when the number of InO_x sub‐cycles in PEALD process was increased from 0.5 to 5 (corresponding to an increase of In atomic ratio from 11% to 50%), confirmed by XPS analyses. Figure 2b presents the normalized transfer curves (I_D –V_G ) of IGZO TFTs with varying In atomic ratios at V_D = 0.1 V. The device was not functional when In was absent in the channel layer. As the In content increased, the TFTs displayed a negative shift in the V_TH . The corresponding key electrical parameters, including V_TH , µ_FE , and subthreshold swing (SS), were extracted from the transfer curves of 20 TFTs each, with excellent standard deviation, demonstrating the reproducibility and fabrication reliability for circuit integration (Figure 2c). The detailed extraction methods for the parameters are provided in Note S1 (Supporting Information). When the In atomic ratio in IGZO films was increased from 11% to 50%, the µ_FE improved from 22.54 to 116.35 cm² V⁻¹·s⁻¹, with a negative V_TH shift from 1.45 to −1.23 V, due to the increased carrier concentration (N_e ) in the In‐rich IGZO films. Additionally, the SS initially decreased from 130.13 mV dec⁻¹ for the IGZO_0.5:1:1 TFTs to 74.60 mV dec⁻¹ for IGZO_1:1:1 , indicating improved switching behavior and reduced trap density. However, as the In content increased further, the SS rose to 92.20 mV dec⁻¹ for the IGZO_5:1:1 sample, suggesting an optimal stoichiometry range beyond which the benefits to switching characteristics are diminished. For comparison, the key performance parameters of TFTs in this work and recent representative ALD‐based IGZO TFTs are summarized in Table 1 , demonstrating the best overall performance despite the low thermal budget. The devices with scaled channel thicknesses down to 4 nm were also characterized, as shown in Figure S3 (Supporting Information). The µ_FE rises from 21.89 cm² V⁻¹·s⁻¹ at IGZO_1:1:1 TFT to 65.63 cm² V⁻¹·s⁻¹ at IGZO_5:1:1 TFT while V_TH moves negatively from 1.31 to −0.14 V, mirroring the trend seen in 10 nm‐thick channels. These observations confirm that the underlying mechanism—namely, In‐driven increases in N_e and V_O defects—is intrinsic to the IGZO material itself and does not depend strongly on film thickness.

Figure 2.

Characterizations and Analyses for IGZO TFTs with different cation ratios. a) The cation atomic percentages in IGZO films with various InO_x sub‐cycle numbers in PEALD process. b) The normalized transfer characteristics of the fabricated IGZO TFTs with various In content. c) The extracted V_TH , µ_FE , and SS of IGZO TFTs with various In content. d) The bandgap of IGZO films with various In content. e) The D_it in IGZO TFTs with various In content. f) The N_e in IGZO films with various In content. g) The O1s XPS spectra of IGZO films with different InO_x sub‐cycle numbers. h) The composition percentages of M‐O, V_O , and ‐OH bonds extracted from O1s XPS spectra.

Table 1.

Benchmark of reported ALD‐based IGZO TFT performance parameters.

Refs.	Year	Temp. budget [°C]	IGZO thickness [nm]	Dielectric/ thickness [nm]	ION /IOFF ratio	SS [mV dec−1]	VTH [V]	µFE [cm2 V−1·s−1]
[37]	2017	250	24.3	Al2O3/100	2 × 109	90	‐	10.4
[38]	2018	180	6	Al2O3/100	—	120	2.57 ± 0.44	15.1 ± 0.53
[39]	2018	250	13	SiO2/100	≈108	300 ± 50	2.41 ± 0.71	22.1 ± 1.3
[35]	2019	450	20	SiO2/100	8.9 × 108	260 ± 20	−1.3 ± 0.2	65.5 ± 1.2
[40]	2019	400	16	SiO2/100	≈107	410 ± 80	−0.51 ± 0.12	36.6 ± 0.3
[41]	2021	500	13	Al2O3/4 + HfO2/50	3.2 × 108	130 ± 10	0.2 ± 0.24	74 ± 0.91
[42]	2021	350	20	SiO2/100	—	360 ± 70	−0.5 ± 0.1	20.1 ± 0.3
[43]	2021	350	20	SiO2/100	—	200 ± 10	0.96 ± 0.07	28.17 ± 0.08
[44]	2021	500	20	HfO2/33	≈104	540	‐	0.19
[45]	2021	500	5	Al2O3/10	—	75 ± 1	−0.07 ± 0.08	34.16 ± 1.93
[46]	2021	200	20	Al2O3/80	—	280	‐	27.6
[47]	2022	400	10	Al2O3/50	—	140 ± 10	−3.09 ± 0.14	52.48 ± 0.31
[48]	2022	350	20	SiO2/100	—	190 ± 10	−1.33 ± 0.16	38.77 ± 1.31
[49]	2022	200	20	Al2O3/45	—	340	1.5	16.3
[50]	2022	200	20	Al2O3/80	—	200	−2.51	36.9
[51]	2023	200	20	Al2O3/40	—	181	—	23.43
[52]	2023	400	10	SiO2/0.7 + HfO2/4	≈108	64 ± 0.5	−0.12 ± 0.01	22.3 ± 0.5
[53]	2023	250	30	SiO2/200	2.2 × 108	200	1.7	8.8
[54]	2023	350	10	Al2O3/20	—	113.5	−0.47	106.5
[55]	2023	600	8	Al2O3/13	—	61	0.05	27.6
[56]	2024	400	21	SiO2/200	4.78 × 106	210	−1.85	38
[57]	2024	300	18.84	Al2O3/50	≈107	150	−0.06	26.5
This work	IGZO0.5:1:1	250	10	HfO2/9	≈108	130.13 ± 4.75	1.45 ± 0.06	22.71 ± 1.56
	IGZO1:1:1	250	10	HfO2/9	≈108	74.60 ± 4.27	0.84 ± 0.09	39.17 ± 2.21
	IGZO3:1:1	250	10	HfO2/9	≈109	86.92 ± 3.93	−0.04 ± 0.05	75.39 ± 2.99
	IGZO5:1:1	250	10	HfO2/9	≈109	92.20 ± 4.59	−1.23 ± 0.05	116.05 ± 4.27

To further support the electrical characteristics and parameter variations in IGZO TFTs with varying cation ratios, we performed UV‐vis‐NIR measurements to evaluate the bandgap of IGZO films, C–V measurements of metal‐oxide‐semiconductor capacitor (MOSCAP) to analyze the interface state density (D_it ) of TFTs, and Hall effect measurements to assess the N_e in IGZO films. Figure 2d presents the bandgap values (including both direct and indirect bandgaps) of the different IGZO films analyzed using UV‐vis‐NIR measurements, with data averaged from five samples each. The bandgap values were calculated through Tauc Plot method,^{[ 28 ]} with details provided in Note S2 (Supporting Information). IGZO is characterized as an n‐type wide bandgap semiconductor exhibiting both direct and indirect optical transitions. As the In content increased from 11% to 50%, the direct bandgap dropped from 3.60 to 3.34 eV, while the indirect bandgap reduced from 2.84 to 2.36 eV, showing a similar trend for both transitions. The bandgap narrowing can be attributed to the content reduction of Ga₂O₃, which inherently has a larger bandgap compared to In₂O₃ and ZnO.^{[ 29 ]} The observed reduction in the bandgap correlates with the negative shift in V_TH , as a narrower bandgap implies that fewer gate‐induced carriers are required to turn on the device. In addition, a smaller indirect bandgap was detected, suggesting the occurrence of indirect band transition caused by the defects formed during the deposition process.^{[ 30} , ^{31 ]} These defects were mainly related to the formation of V_O and interstitial atoms in IGZO films. In addition, the energy difference between the direct and indirect bandgap was calculated to estimate changes in defect transition levels. An increase in energy difference from 0.76 to 0.98 eV indicated a higher concentration of V_O , contributing to the improved µ_FE .

The SS of IGZO TFTs is largely determined by trap states at the dielectric‐semiconductor interface, which act as additional capacitances that must be charged before the channel is modulated. The D_it quantifies the density of these trap states per energy interval; a high D_it implies that an applied gate voltage (V_G ) initially fills these states rather than shifting the surface potential, thereby degrading SS. In this study, the observed trends in the SS of the different IGZO TFTs were elucidated using D_it analyses shown in Figure 2e, evaluated separately using two different methods. The one was directly calculated from SS, with equation given by:

$$D_{it}=\frac{C_i}{q}\left[\frac{SS·log\left(e\right)}{\left(kT/q\right)}-1\right]$$ (1)

Where C_i is the unit‐area capacitance of gate dielectric, k is the Boltzmann constant, q is elementary charge, and T is the ambient temperature.^{[ 32 ]} The other was obtained through high‐ and low‐frequency capacitance measurement (Castagne‐Vapaille method),^{[ 33 ]} with equation given by:

$$D_{it}=\frac{1}{qA}\left(\frac{C_{ox}{C}_{lf}}{C_{ox}-C_{lf}}-\frac{C_{ox}{C}_{hf}}{C_{ox}-C_{hf}}\right)$$ (2)

where C_ox is the oxide capacitance, A is the area of MOSCAP, C_lf and C_hf are the capacitances of MOSCAPs at low frequency and high frequency, respectively. The C–V curves of the IGZO MOSCAPs with various In content are shown in Figure S4 (Supporting Information), where the voltage switching points of the C–V curves are consistent with the V_TH of the corresponding TFTs. The energy‐dependent D_it calculated from the C–V characteristics of IGZO devices with different In contents shows the similar trend of the SS results (Figure S30, Supporting Information). The details of this approach are provided in Note S3 (Supporting Information). The D_it values calculated using both evaluation methods exhibited similar trends (as shown in Figure 2e), confirming the change in D_it of the IGZO TFTs in affecting the SS values. The D_it values calculated from C–V measurements were lower than that obtained from SS, which was because the frequency in the low‐frequency C–V measurement, limited by the testing equipment, was not sufficiently low, leading to some interface traps being unable to respond to the AC signal during the measurements. Figure 2f shows the variation trend of N_e measured through a Hall effect system with van der Pauw measurement geometry. As the In content increased from 11% to 50%, the N_e in IGZO films rose by approximately four orders of magnitude, from 4.76 × 10¹⁶ to 1.01 × 10²⁰, largely attributed to the increased unoccupied 5s orbitals with increasing In content, contributing to a lower electron effective mass and enhancing electron mobility.^{[ 34} , ^{35 ]}

Further XPS measurements for the different IGZO films are shown in Figure 2g. The O1s peaks were deconvoluted into three distinct sub‐peaks corresponding to the different oxygen species. These included a peak at lower binding energy centered at ≈529.9 eV (magenta curve), corresponding to lattice oxygen or metal‐oxygen (M─O); a peak at medium binding energy centered at ≈530.9 eV (blue curve), associated with V_O ; and a peak at higher binding energy centered at ≈531.9 eV (green curve), corresponding to certain impurities such as hydroxyl groups (‐OH).^{[ 36 ]} The calculated relative area ratios of the M─O, V_O , and ‐OH bonds for different IGZO films are shown in Figure 2h. As the In content in IGZO films increased, the relative proportion of M─O decreased while the V_O increased, with no significant variation in the ‐OH. This behavior stems from In's larger ionic radius and weaker In‐O bond energy, which destabilize the oxide network and promote V_O formation. In oxide semiconductors, V_O is generally regarded as the source of shallow donor states that contribute to charge carrier generation. Consequently, the increase of V_O content directly results in a higher N_e and improved mobility. In summary, all the evidence points to the increase of In content within the IGZO films leading to a higher density of V_O , thereby elevating N_e and enhancing µ_FE , highlighting the critical role of compositional tuning in optimizing the electrical properties of IGZO TFTs.

The long‐term reliability, voltage‐bias, and temperature‐bias stability of the optimized IGZO TFTs were also assessed. As depicted in Figure S5 (Supporting Information), the devices exhibited negligible change after 120 days in a humid‐air environment despite the absence of channel encapsulation. Under positive bias temperature stress (PBTS), they displayed a negligible positive V_TH shift (ΔV_TH ) of 0.07 ± 0.03 V, and under negative bias temperature stress (NBTS), a small negative ΔV_TH of −0.15 ± 0.05 V was observed over 3600 s (Figure S6, Supporting Information). Under temperature bias, the devices exhibited modest ΔV_TH ≈ −0.14 V at 80 °C and ‐0.65 V at 120 °C, and these shifts are fully reversible upon cooling back to room temperature (Figure S7, Supporting Information). Hence, we demonstrated that with proper material properties modulation and deposition technique, both performance and reliability over multiple devices can be achieved concurrently for circuits implementation presented in the following sections. In addition, the advantages of PEALD IGZO deposition process compared with sputter process is supplemented in Note S4 (Supporting Information). The influence of PEALD process parameters on IGZO TFT properties were also systematically investigated, and supplemented in Note S5 (Supporting Information). The contact resistance (R_C ) was also evaluated via the transfer length method (TLM) to assess its impact on mobility, as detailed in Note S6 (Supporting Information).

2.3. IGZO TFT Modeling

To extend the applications of IGZO TFTs to the logic circuit level, a TCAD device model using Sentaurus was developed to accurately capture the unique DC characteristics of IGZO TFTs. In this work, the IGZO_1:1:1 TFT was chosen for our device Modeling and circuit‐level simulations because it offers a well‐balanced performance, that is, a modest mobility (39.17 cm² V⁻¹·s⁻¹) together with a positive V_TH (0.84 V) and small SS (74.60 mV dec⁻¹). While mobility is an important performance metric, a positive V_TH is especially important to eliminate high off‐state leakage and standby power. Considering the reasonably good mobility and desired positive V_TH , our choice of IGZO_1:1:1 provides an optimal balance for low‐power digital design, ensuring both noise margin and leakage control. In addition, the strategies to mitigate the V_TH shift in high‐mobility compositions is discussed in Note S7 (Supporting Information). Figure 3a exhibits the normalized transfer curves (I_D –V_G ) of 120 fabricated IGZO_1:1:1 TFTs at V_D = 0.1 V. The I_D –V_G clusters show good uniformity and small V_TH variation. Figure 3b–d shows the statistical histograms of the extracted parameters of V_TH , µ_FE , and SS from all the devices, exhibiting gaussian distributions with the mean value (µ) and standard deviation (σ) labelled. These electrical parameters served as the foundation for device Modeling, with details provided in the “Experimental Section”.

Figure 3.

IGZO TFT Modeling. a) The normalized transfer curves (I_D –V_G ) of 120 fabricated IGZO TFTs. b–d) The statistical histograms of the extracted V_TH , µ_FE , and SS from the120 devices, with the Gaussian fit curves. e,f) Experimental (symbols) and simulated (solid lines) transfer and output characteristics of the IGZO TFT, with an inset in e) showing linear scale plots.

Figure 3e,f displays the experimental (symbols) and simulated (solid lines) transfer and output characteristics of the IGZO TFTs. The excellent agreement between the experimental and simulated results were achieved after the extracted V_TH , µ_FE , SS, physical and geometrical parameters were fed into the model. The experimental and simulated families of I_D –V_G curves (V_D : 0.1 to 1 V, step: 0.1 V) for the IGZO_1:1:1 TFT are shown in Figure S8 (Supporting Information), showing both logarithmic‐scale and linear‐scale plots to clearly exhibit the fitness of curves in subthreshold and saturation regions.

2.4. Simulation and Experimental Demonstration for IGZO TFT‐Based Inverter

Inverter serves as the fundamental building block in digital logic circuits. Utilizing the calibrated TFT model, two inverter configurations—namely, PEL and EL—were designed and systematically evaluated. The circuit diagrams and corresponding optical micrographs of both inverters are presented in Figure S9 (Supporting Information). The voltage transfer curves (VTCs) were optimized through simulation by adjusting the TFT parameters (i.e., W_CH and L_CH ) to achieve the best voltage gain and noise margin (NM) for each configuration, with the optimized dimensions summarized in Table S1 (Supporting Information). Figure 4a,b compares the simulated and experimentally measured VTCs of the PEL and EL inverters, showing excellent agreement. Both simulations and experiments were performed at V_DD = 1.5 V, while V_Bias was varied from 2 to 3.5 V in step of 0.5 V. Under a constant V_DD , the VTCs exhibited a positive shift as V_Bias increased, primarily due to the increasing V_IM , which reduced the impedance of transistor T₃ (see Figure S9, Supporting Information). The EL inverters functioned, but did not achieve rail‐to‐rail operation due to the finite load impedance of the pull‐up transistor (T₁ ). In contrast, the PEL inverters achieved rail‐to‐rail operation, switching V_OUT from V_DD to near 0 V (V_SS ) owing to the inclusion of a second stage that formed a pseudo‐CMOS structure, thereby increasing the overall load impedance of the pull‐up transistor.

Figure 4.

Simulation and experimental demonstration of IGZO TFT‐based inverter. a,b) The simulated and experimentally measured VTCs of the PEL and EL inverters at V_DD of 1.5 V and V_Bias varying from 2 to 3.5 V in voltage step of 0.5 V. c,d) The corresponding voltage gains of the PEL and EL inverters, extracted from VTCs. e,f) The corresponding noise margin (NM) of the PEL and EL inverters, extracted from VTCs.

Figure 4c,f presents the voltage gain and NM (both derived from the VTCs) for the PEL and EL inverters. The gains of both inverters decreased as V_Bias increased from 2 to 3.5 V, attributed to the reduced impedance of the pull‐up transistor (T₁ ) with increasing V_Bias . The PEL inverters achieved a low noise margin (NM_L ) of 0.46 V and high noise margin (NM_H ) of 0.47 V at V_DD = 1.5 V and V_Bias = 3 V, while the EL inverters achieved a NM_L of 0.10 V and NM_H of 0.43 V at V_DD = 1.5 V and V_Bias = 2 V. The PEL inverters exhibited a larger gain and NM compared to EL inverters, primarily attributed to the pseudo‐CMOS structure at the cost of doubling the number of TFTs. Additional VTCs and gains for both inverters under varying V_DD are shown in Figures S10 and S11 (Supporting Information). A benchmark table (Table S2, Supporting Information) summarizes key parameters of the two inverters, confirming that the PEL configuration offers superior robustness due to its two‐stage pseudo‐CMOS structure.

2.5. Experimental Demonstration and Projection for IGZO TFT‐Based Ring Oscillator

To explore the merits and potential of high‐performance IGZO TFTs at the circuit level, we designed and experimentally demonstrated 5‐stage ROs based on both PEL and EL inverters. The circuit diagram and optical micrographs of the fabricated ROs are presented in Figure S12 (Supporting Information). Figure  5a,b shows the experimentally measured and simulated output waveforms of the PEL inverter‐based 5‐stage RO at V_DD = 1.5 V and V_Bias = 3.5 V, respectively. The measured oscillation frequency of the PEL inverter‐based RO was 443.5 kHz, whereas the simulated frequency was 463.2 kHz. By contrast, the measured oscillation frequency of the EL inverter‐based RO was 324.9 kHz, and the simulated value was 323.9 kHz (as shown in Figure S13, Supporting Information). Although the PEL inverter‐based RO required twice as many TFTs and therefore incurred a larger area penalty, they achieved a higher oscillation frequency compared to the EL inverter‐based RO, which can be attributed to the higher voltage gain of the PEL inverters. To validate the robustness of the simulation results, 1000 Monte Carlo simulations were performed for the PEL inverter‐based RO, with the amplitude and frequency distributions shown in Figure S14 (Supporting Information). The measured oscillation frequencies closely matched the corresponding simulation values for both two types of ROs, when considering the parasitic capacitances existed in the fabricated ROs. However, in practical integrated circuit design and manufacturing, such parasitic capacitances are substantially reduced—commonly below 0.1 pF—by minimizing unnecessary wiring and contact pads. To evaluate the true performance of the proposed RO, the oscillation frequency as a function of parasitic capacitance was projected; the oscillation frequency of the IGZO TFT‐based RO can reach ≈21.1 MHz when the parasitic capacitance is projected to 0.1 pF (Figure 5c).

Figure 5.

Experimental demonstration and projection for IGZO TFT‐based ring oscillator. a,b) The experimentally measured and simulated output waveforms of the PEL inverter‐based 5‐stage RO, respectively, showing good agreement. c) Projected oscillation frequency as a function of parasitic capacitance in the PEL inverter‐based RO. d) Projected VTCs of inverters across various technology nodes. e Projected oscillation frequency for ROs across various technology nodes.

To further evaluate the scalability of the proposed ROs at more advanced technology nodes, we performed projections based on the calibrated TCAD device model. The projected VTCs of inverters at various technology nodes are shown in Figure 5d, while Figure 5e plots the corresponding predicted frequencies of RO (the corresponding output waveforms shown in Figure S15, Supporting Information). As technology nodes advance, the achievable frequency increases markedly, surpassing 240 MHz at the 22 nm node. These findings demonstrated that the operating frequency of IGZO TFT‐based RO can be substantially improved through both parasitic‐capacitance reduction and technology scaling, underscoring the promise of IGZO TFTs for high‐speed electronic applications. The performance metrics for recently reported oxide‐based ROs are summarized in Table S3 (Supporting Information). Our proposed ROs achieved largest voltage swing (88%) and oscillation frequency (443.5 kHz) at lowest V_DD (1.5 V), which can be attributed to the excellent performance of the optimized IGZO TFTs.

2.6. Experimental Demonstration and Simulation for IGZO TFT‐Based SRAM

To further explore the potential of high‐performance IGZO TFTs at the logic circuit level, we designed and experimentally demonstrated a SRAM cell based on PEL inverters, a critical module in all CMOS technology nodes. The typical 6‐T SRAM architecture was employed, comprising two cross‐coupled PEL inverters and two access transistors (T_C1 , T_C2 ), as depicted in Figure S16 (Supporting Information). The device dimensions, particularly the W_CH and L_CH of the transistors within SRAM cell, are critical parameters that influence both the read/write operations and overall stability. Specifically, a higher drivability of the pull‐down transistors (T_A2 , T_B2 ) relative to the access transistors is necessary for robust read operations, whereas a lower drivability of the pull‐up transistors (T_A1 , T_B1 ) compared to the access transistors is preferred for efficient write operations.^{[ 58 ]} These channel dimensions were optimized through simulations in Sentaurus, and the resulting optimized TFT sizes are summarized in Table S4 (Supporting Information).

The static characteristics of the SRAM cell—including the hold static noise margin (HSNM), read static noise margin (RSNM), and write static noise margin (WSNM)—serve as critical indicators of its stability and sensitivity. A high HSNM value of 0.45 V, which corresponds to 60% when normalized by V_DD /2, was achieved, indicating excellent stability of the SRAM cell in its data hold state (Figure 6a). A RSNM value of 0.26 V (34.67%, normalized by V_DD /2) was achieved, confirming that the cell can reliably output one‐bit binary data during read operations (Figure 6b). A WSNM value of 0.25 V (33.33%, normalized by V_DD /2) was realized, demonstrating that one‐bit binary data can be stably written into the cell (Figure 6c). Additionally, the N‐curve method was also employed to further evaluate the read/write performance (Figure S17, Supporting Information). The detailed evaluation methods and analyses for HSNM, RSNM, WSNM and N‐curve, are supplemented in Note S8 (Supporting Information). Although only n‐type TFTs were used in the SRAM, all the static characteristics, including HSNM, RSNM, and WSNM, exhibited large values and good robustness, which can be attributed to the high performance of optimized IGZO TFTs and pseudo‐CMOS structure of inverters. To further evaluate the static characteristics of the proposed SRAM at advanced technology nodes (extending down to a 22 nm dimension), we conducted simulations using Sentaurus to assess the HSNM, RSNM and WSNM (Figures S18–S20, Supporting Information). The static characteristics exhibited optimal performance at the 65 nm node, but deteriorated with further scaling (Figure S21, Supporting Information). This behavior originated from pronounced short‐channel effects in sub‐65 nm devices which degraded the SS and induced V_TH drift, consequently flattening the slope of the inverter's VTC and reducing the SRAM noise margin (Figure S22, Supporting Information).

Figure 6.

Static and dynamic characteristics of IGZO TFT‐based SRAM. a–c) The VTCs and extracted static noise margin (SNM) during hold, read, and write operations. d) Dynamic response of the SRAM during continuous write and hold operations. e) Simulated dynamic characteristic during continuous write and read operations.

The dynamic characteristics were also evaluated. Figure 6d illustrates the dynamic response during write and hold operations at a bit line (BL) frequency of 250 Hz. In this test configuration, when the word line (WL) was enabled (the WL voltage was set to V_DD ), the cell could update the stored data at Q and QB nodes reliably. Conversely, when the WL was disabled (the WL voltage was set to GND), the cell effectively retained the stored logic “0” or “1,” demonstrating robust data hold capability. During write operations, the switching time measured was 97 µs (Figure S23, Supporting Information), whereas simulations projected a reduction to as low as 0.78 ns at the 22 nm node (Figure S24, Supporting Information). Due to measurement limitations, the dynamic response of the read operation was characterized through simulation using Sentaurus. To enable sequential write and read operations, the SRAM cell requires peripheral circuits, specifically the pre‐charge and write‐driver modules. As illustrated in Figure S25 (Supporting Information), the write‐enable signal (WE) controls the write operation, while the pre‐charge signal (PRE) determines the execution of the pre‐charge process. To compensate for threshold voltage loss, the voltages of both PRE and WE were elevated to V_DD + V_TH . Figure 6e exhibits the simulated dynamic response during continuous write and read operations, and the simulated timing sequence is described in details in Note S9 (Supporting Information). The designed SRAM cell exhibited excellent performance in both static and dynamic evaluations. Table S5 (Supporting Information) presents the performance comparison between our proposed design and several state‐of‐the‐art SRAMs, demonstrating that our approach achieved optimal overall performance at the lowest V_DD , despite with a unipolar TFT design. In addition, the limitations in scaling IGZO TFTs for dense logic circuits are discussed in Note S10 (Supporting Information), while the discussion of the M3D integration are expanded in Note S11 (Supporting Information).

3. Conclusion

In summary, we provided a comprehensive assessment of PEALD IGZO TFTs, as well as its derived functional circuitries suitable for M3D integration. At the device level, an exceptional µ_FE up to 116.35 cm² V⁻¹·s⁻¹, outstanding long‐term reliability, and excellent voltage‐bias stability of ΔV_TH less than 0.15 V were achieved. All the device improvement mechanisms were supported via extensive material characterization—including UV absorption, Hall effect measurements, C–V measurements, and XPS analyses. To enable unipolar TFT‐based circuit design, a TCAD model for the optimized IGZO TFT was established via Sentaurus. Both PEL and EL inverters were simulated and experimentally validated using the established device model, achieving excellent agreement between simulation and measurement. We then presented 5‐stage ROs design framework based on both inverter configurations with functional experimental demonstration. We also demonstrated the design and experimental characterization of a unipolar SRAM based on PEL inverters for the first time, exhibiting excellent static and dynamic characteristics, although with the use of n‐only TFTs. Finally, to account for their implementation feasibility at advanced technology node, we provided the performance projection of the 5‐stage RO and SRAM cell down to the 22 nm node, with the RO oscillation frequency potentially reaching a high 240 MHz, and SRAM switching time down to a remarkable 0.78 ns with excellent noise margins. Our results, encompassing IGZO TFT performance optimization, device Modeling, circuit design framework, circuit demonstration and technology projection roadmap, are expected to offer valuable guidance for the future integration of IGZO TFT‐based circuitry at CMOS BEOL.

4. Experimental Section

Device Fabrication

The IGZO TFTs and circuits were fabricated on the SiO₂/Si substrate. The fabrication process started with the standard cleaning steps with the SC‐1 and SC‐2, followed by ultrasonic cleaning using acetone and isopropyl alcohol (IPA). The bottom‐gate electrode, composed of Ti and Pt with thickness of 3.6 and 15 nm respectively (as confirmed by TEM imaging), was first deposited using a DC sputtering system (PVD75, Kurt J. Lesker) onto a p⁺‐doped Si substrate coated with 285 nm‐thick thermally oxidized SiO₂ layer. The Argon (Ar) was used as carrier gas, and the working pressure was set as 3 mTorr (corresponding the Ar flow of 12.4 sccm). The sputtering powers of Ti and Pt were set as 120 and 100 W, respectively. The film growth rates of Ti and Pt were 0.56 and 1.38 Å s⁻¹, respectively. Then, a 9 nm‐thick HfO₂ layer was deposited as the gate dielectric by thermal atomic layer deposition (ALD) over 100 cycles, using tetrakis (dimethylamino) hafnium (TDMAH) as the Hf precursor and H₂O as the reactant respectively at 250 °C. In the ALD process for HfO₂, the pulse time and purge time for TDMAH were set to 0.1 and 20 s, while those for H₂O were 0.06 and 40 s, respectively. The carrier gas (99.999% N₂) flow rates for TDMAH and H₂O were set as 200 sccm. The TDMAH source bottle was maintained at 65 °C, while H₂O source was kept at room temperature during the deposition. Next, the 10 nm‐thick IGZO active channel layer was deposited using PEALD at 200 °C. In the PEALD process, the (3‐dimethylamino‐propyl) dimethyl indium (DADI), trimethyl gallium (TMGa), and diethyl zinc (DEZ) were used as In, Ga and Zn precursors respectively, while oxygen plasma was used as reactant. The DADI source bottle was heated to 80 °C, while TMGa and DEZ source bottles were kept at room temperature during the process. The pulse time and purge time for DADI, TMGa and DEZ were set to 0.05 and 40 s, respectively. The carrier gas (99.999% N₂) flow rates for DADI, TMGa and DEZ were set to 200 sccm. The O₂ flow rate was set to 200 sccm, while the plasma power was set as 500 W. The stay time and purge time for oxygen plasma were set to 20 and 15 s, respectively. Both the HfO₂ gate dielectric and IGZO channel regions were defined via standard lithography followed by a buffered oxide etch (BOE) etching process. The BOE etching rates for HfO₂ and IGZO layers were ≈0.1 and 1 nm s⁻¹ through calibration, respectively. After that, the source/drain electrodes (comprising 20 nm Ti and 26 nm Au) were deposited using DC sputtering followed by a lift‐off process (same as the bottom gate). The sputtering power of Au was set as 50 W, while the film growth rate was 1 Å s⁻¹. Finally, pad opening for devices and circuits was conducted through standard lithography followed by BOE etching.

The fabrication process for the proposed ROs and SRAM cell closely followed that of IGZO TFTs, with one additional process step: the incorporation of an additional inter‐layer deposition of a 75 nm‐thick SiO₂ layer, deposited using RF sputtering, between the overlapping bottom and top metal interconnects. This additional process step is critical for ensuring the proper insulation and performance of the integrated device structure.

Characterizations and Measurements

All film thicknesses and the refractive indices of IGZO films were measured using an ellipsometer (TF‐UVISEL). The channel surface roughness was measured using AFM (Dimension Edge). Cross‐sectional observation of TFT gate stack was performed with TEM (Talos F200X G2), operating at 120 kV. The cross‐sectional specimens of IGZO TFT stack for TEM measurement were prepared via focused ion beam (FIB) (Helios 5 CX). The crystallinity of IGZO films was analyzed using GI‐XRD (Rigaku Smartlab) under parallel beam (PB) optical path mode, in which the grazing incidence was set as 0.5° while the voltage and current for X‐ray were 40 kV and 150 mA, respectively. The chemical bonding and elemental compositions were analyzed using XPS (ESCALAB 250Xi), with monochromatic Al Kα X‐ray source. The absorption spectra of IGZO films (deposited on quartz substrate) were measured using UV‐vis‐NIR Spectrometer (PerkinElmer Lambda 950).

The carrier concentrations of IGZO films were measured using a Hall effect system (Nanometrics HL5500PC), with van der Pauw measurement geometry. Current–voltage (I–V) characteristics of IGZO TFTs, capacitance–voltage (C–V) curves of Metal‐HfO₂‐IGZO‐Metal MOSCAP structure, VTCs of all inverters and SNMs of SRAM cells were measured with a semiconductor parameter analyzer (Keithley 4200‐SCS) at room temperature under ambient conditions. The output waveforms of ROs and dynamic responses of SRAM cells were measured using an oscilloscope (Tektronix MSO64B). The rectangular waves for write operation of SRAM were generated by a signal generator (Tektronix AFG1022).

TCAD Modeling

All simulations were performed using Sentaurus. IGZO was modelled as a bulk semiconductor and channel transport approximated via the drift‐diffusion method. Band tail states were incorporated to accurately represent the doping conditions in IGZO. The onset of the doping‐dependent mobility feature was used to account for mobility degradation resulting from carrier scattering by charged impurity ions within IGZO. Additionally, the carrier velocity saturation phenomenon in short‐channel devices under high electric fields was captured using the Canali model^{[ 59 ]} based on the Caughey‐Thomas formulation.^{[ 60 ]} Material parameters were iteratively tailored to fit the measured transfer and output characteristics until the on‐state performance error was reduced to less than 1%, and the results presented in Table S6 (Supporting Information). The details of the TCAD device model calibration are supplemented in Note S12 (Supporting Information).

Circuits Simulation

With the calibrated TCAD model for IGZO TFTs, the impact of device scalability on circuit‐level performance was systematically investigated by shrinking the channel length from 5 µm to 22 nm. Benchmark circuits, including a 5‐stage RO and a 6T SRAM, were simulated using mixed‐mode in Sentaurus Device. For the 5‐stage RO, oscillation frequencies were extracted from transient simulation results as a function of technology node, with a load capacitor introduced at each stage to model the lumped parasitic effects of interconnects. To accommodate scaling‐induced changes, the load capacitor values were dynamically adjusted for each technology node; the initial parasitic capacitor value for the 5 µm node was determined through calibration against experimental data, and the corresponding supply voltages and load capacitor values for each node are presented in Table S7 (Supporting Information). For the SRAM circuit, both transient and quasistationary simulations were performed. The dynamic read and write operations were analyzed via transient simulation, while the hold, read, and write SNM were evaluated through quasistationary analysis.

Conflict of Interest

The authors declare no conflict of interest.

Supporting information

Supporting Information

Wang W., Zhang T., Yuan Z., et al. “Device to Circuit Co‐Design Utilizing High‐Performance PEALD Indium‐Gallium‐Zinc Oxide Thin‐Film Transistor Enabling Technology Node Scaling in Monolithic 3D Systems.” Adv. Sci. 13, no. 6 (2026): e10551. 10.1002/advs.202510551

Data Availability Statement

The data that support the findings of this study are available from the corresponding author upon reasonable request.