Scalable Ising machine composed entirely of Si transistors

Abstract

We introduce a complementary metal-oxide semiconductor (CMOS) Ising machine (CIM) composed entirely of silicon-based metal-oxide semiconductor field-effect transistors (MOSFETs). Instead of adhering to the conventional functions of MOSFETs as switches or amplifiers, CIM adopts an unprecedented approach that uses the dual characteristics of MOSFETs to function as both oscillators and couplers, enabling the coupling strength between oscillators to be tuned through gate biasing. These dual behaviors facilitate effective synchronization within the CIM, while the use of MOSFETs ensures full compatibility with standard CMOS fabrication technology and provides a pathway toward scalable hardware implementation. We also address the challenge of frequency variability, a critical issue in a large-scale CIM, by finely tuning the gate voltage of the oscillating transistors. This strategy notably enhances the stability and reliability of the CIM, achieving a level of control that is difficult to attain in other Ising machines using heterotypic device architectures. This CIM was applied to solve a MaxCUT problem. The demonstrated advantages of our CIM, including its compact cell size, high scalability, and robust operation, represent a promising direction for the advancement of future large-scale and energy-efficient Ising machines.

A highly scalable and reliable CMOS Ising machine, entirely composed of silicon-based transistors, is demonstrated.

INTRODUCTION

Combinatorial optimization, a method that aims to find the minimum of an objective function within a large set of candidate solutions, is crucial in various industries including transportation and telecommunications. While specialized algorithms exist for specific cases, most real-world combinatorial optimization problems (COPs) remain intractable because of their complexity and the vast computational load, and require additional steps for conventional optimization methods (1, 2). Conventional heuristic methods for solving COPs rely on von Neumann architectures, which lead to an exponential growth in resources as problem size increases. As an alternative, an Ising machine has been proposed as a specialized hardware system to accelerate the solution of nondeterministic polynomial-time hard COPs, making it valuable in diverse fields such as autonomous vehicles, layout design, and drug discovery.

To date, the spin-based Ising model has been extensively studied for solving COPs, thanks to its inherent computational efficiency when handling such problems (3, 4). The Ising model consists of binary spin states connected by a coupling matrix, as shown in Fig. 1A. The Ising model provides a framework for identifying the spin configuration that minimizes the Ising Hamiltonian, effectively mapping COPs onto an energy minimization process. Ising machines have been developed using various technological approaches, including static random-access memory (SRAM)–based annealers implemented with complementary metal-oxide semiconductor (CMOS) technology (5, 6), quantum annealers (7, 8), and optical systems (9–11), each of which relies on distinct physical principles to perform optimization tasks. However, SRAM-based annealers, while benefiting from CMOS compatibility and room-temperature operation, are limited by their large footprint, as each SRAM cell consists of six metal-oxide semiconductor field-effect transistors (MOSFETs). Quantum annealers require ultralow temperatures, resulting in high operational costs, whereas optical coherent Ising machines suffer from structural complexity and limited scalability.

Fig. 1. Concept of all-MOSFET Ising machine.

(A) Spin-based Ising model. COPs can be mapped to an Ising model. (B) OIM comprising N_osc and couplers. There are two major limitations in conventional large-scale OIMs using CMOS circuits. One is the need for a large number of transistors and the other is f_osc variations between oscillators. The proposed CIM consists of oscillating transistors (1T-Os) and coupling transistors (1T-Cs). (C) Operation of the 1T-O and 1T-C. (D) Schematic of the 1T-O coupled through 1T-C. The proposed CIM significantly reduces the number of transistors compared to circuit-based oscillators, thereby reducing footprint area, improving energy efficiency, and solving COPs accurately.

As another approach, oscillator-based Ising machines (OIMs) have attracted interest because of their simple architecture and inherent stochasticity, which enable the efficient exploration of complex energy landscapes (12–18). In general, an OIM processes signals based on the phase of oscillations instead of relying on the signal amplitude, and this is advantageous in terms of energy consumption. This feature is even more pronounced as the system size increases. In OIMs, the spin states in the Ising model are represented by individual oscillators, while spin interactions are modeled as coupling strengths between oscillators, as shown in Fig. 1B. Moreover, subharmonic injection locking (SHIL) has been used in OIMs to facilitate the identification of optimized solutions by constraining oscillator phases to two distinct states (19–21). These machines exploit the collective dynamics of coupled oscillators to naturally converge toward the global minima of the energy function.

However, despite their potential, existing OIMs are presently limited by their scalability and power efficiency. As the number of oscillators (N_osc) increases, the number of required couplers grows quadratically, leading to a substantial rise in configurational complexity. Previous CMOS-based OIMs use ring oscillators as the oscillating elements and use complex circuitry for coupling, which necessitates a large number of MOSFETs (13) and imposes constraints on both chip area and total energy consumption. The conventional use of MOSFETs as switches or amplifiers constrained prior efforts to consider them as standalone oscillators, thereby precluding the proposal to replace a ring oscillator with a single MOSFET. In response, alternative OIM architectures were introduced, which depart from CMOS technology, using metal-insulator transition (MIT) oscillators (22, 23). This approach offers advantages in terms of energy consumption by realizing oscillatory behavior using only a single MIT-based oscillator without relying on circuitry. However, the coupler used to connect multiple MITs poses challenges to miniaturization, large-scale integration, and CMOS compatibility. These challenges arise from the use of heterotypic resistors or capacitors, which are structurally different from MIT devices.

At the same time, prior implementations of OIMs have exhibited limited reconfigurability because they do not allow dynamic tuning of coupling strengths, which is an essential feature for a wide range of Ising model configurations (24). In particular, the requirement to dynamically adjust the coupling strength depending on the scale of connections remains a substantial challenge in reconfigurable hardware design. Another critical issue arises from frequency (f_osc) variations among oscillators. As the number of coupled oscillators increases, their natural frequencies interact, resulting in phase dispersion that complicates the differentiation of spin states. While SHIL has demonstrated effectiveness in small-scale systems, difficulties arise in large-scale OIMs with complex Ising model connectivity. If the f_osc variations exceeds the locking range of the injection signal, the system fails to solve the COPs correctly.

To address the limitations of existing OIMs, we present a highly scalable CMOS Ising machine (CIM) composed entirely of MOSFETs, using an industry-comparable structure with a footprint of 4F². This work presents a demonstration of CIM that uses a single MOSFET as an individual oscillator and another as a coupler, thereby simplifying the overall design and enhancing scalability. As shown in Fig. 1C, each transistor-based oscillator (1T-O) represents an individual spin state, and each transistor-based coupler (1T-C) with adjustable frequency serves to regulate the strength of interaction between spins, effectively emulating spin-to-spin coupling. In the proposed CIM, the 1T-Os use vertical silicon pillars protruding from a silicon wafer as channels, each fully surrounded by a gate in what is known as a gate-all-around (GAA) structure. The 1T-C uses a planar silicon channel that serves as the floating body (FB), with the gate positioned above it. In this work, the vertically structured 1T-Os and the planar 1T-Cs were fabricated separately and connected using wire bonding for the characterizations. In future work, monolithic integration through vertical stacking will be used by fabricating the 1T-Cs using thin-film transistors with polycrystalline silicon channels directly above the vertical 1T-Os to further enhance packing density for very large-scale integration. The vertical stacking of MOSFETs for such monolithic integration has already been commercially realized in vertical NAND flash memory under architectures known as “cell over periphery” or “periphery under cell.” Thus, this approach aligns with, rather than contradicts, Jack Kilby’s original concept of the integrated circuit.

Figure 1D presents a conceptual schematic of the coupled 1T-Os through 1T-C. Unlike other devices used in Ising machines, the 1T-O regulates f_osc through gate voltage (V_G,1T-O), enabling a compact and energy-efficient design. Furthermore, we demonstrate that tuning V_G,1T-O allows precise adjustment of f_osc, effectively reducing frequency dispersion in large-scale CIMs and thereby improving system solvability. The results confirmed the robustness of this approach in mitigating frequency dispersion and maintaining reliable phase synchronization across the CIM.

On the other hand, the 1T-C modulates the coupling strength between connected 1T-Os by adjusting its channel conduction state via its gate voltage (V_G,1T-C), in contrast to passive devices such as resistors and capacitors, which lack external tunability. The use of an active device such as an MOSFET to achieve tunable coupling strength also distinguishes this approach from previous work that reported a reconfigurable coupled oscillator platform based on CMOS circuits (25). This functionality enables reconfigurable operation of the CIM across diverse applications by supporting multiple levels of coupling strength, thereby facilitating highly flexible connectivity within the system. In addition, unintended current paths, commonly known as sneaky paths between adjacent elements in the arrayed CIM, are effectively suppressed. This is attributed to the use of three-terminal MOSFET-based 1T-Os and 1T-Cs, whose structural configuration inherently prevents leakage currents and parasitic bypasses compared to two-terminal devices. Last, to validate the feasibility of the proposed CIM, using SHIL, we solved the MaxCUT problems through both hardware experiments for a small-scale case and semiempirical simulations for a large-scale scenario.

RESULTS

Characteristics of a 1T-O

The n-channel 1T-Os were fabricated using standard CMOS fabrication technology. To minimize the footprint area, a vertical MOSFET structure with a layout of 4F² was designed. In addition, a GAA configuration was devised to effectively confine holes to sustain oscillations. Figure 2A presents a schematic of the 1T-Os; Fig. 2B shows a scanning electron microscopy (SEM) image of the fabricated 1T-O array, and Fig. 2C presents a cross-sectional transmission electron microscopy (TEM) image of a single 1T-O. Each 1T-O is composed of an n⁺ source (S) at the top, a p-type FB in the middle, and an n⁺ drain (D) at the bottom. The p-type FB is fully surrounded by a gate (G). The diameter and height of the silicon pillar are 400 and 700 nm, respectively. The detailed fabrication processes are explained in fig. S1. This vertical structure inherently provides an FB due to the GAA configuration, while also enabling scalability, high integration density, and the realization of large-scale CIM (26, 27).

Fig. 2. Measured characteristics of 1T-O.

(A) Schematic illustration of the 1T-O array with a vertical pillar channel surrounded by a gate. (B) SEM image of the vertical 1T-O array. (C) TEM image of the vertical 1T-O. (D) Energy band diagram for the 1T-O. The energy barrier height between source and FB (V_bi,S-FB) is controlled by its gate voltage (V_G,1T-O). (E) Measured output characteristic (I_D-V_D) of the 1T-O for various V_G,1T-O. At V_LU, I_D was abruptly increased from HRS to LRS. The value of V_LU was also adjusted by V_G,1T-O. (F) Measured oscillating V_out of the 1T-O for various V_G,1T-O. V_out oscillates between V_top and V_bot. (G) Measured latch-up voltage (V_LU) and oscillation frequency (f_osc) of the five 1T-Os for various V_G,1T-O.

Figure 2D illustrates the energy band diagram along the vertical depth direction. The FB is physically isolated by the S/D and electrically confined by the built-in potential (V_bi,S-FB) at the S-FB junction and the built-in potential (V_bi,D-FB) at the D-FB junction along the vertical direction. The FB is also completely surrounded by the gate dielectrics due to its GAA structure. When a drain voltage (V_D) is applied to the D, the V_bi,D-FB is enlarged sufficiently to initiate impact ionization (II) near the D, leading to the iterative generation of electron-hole pairs. The generated holes momentarily accumulate in the FB, reducing the V_bi,S-FB and thereby increasing the injection of electrons from the S toward the FB, which further enhances II. The generated electrons add to the injected electrons, amplifying the II process further. This cycle of carrier generation, accumulation, and reinforcement continues as a positive feedback loop until all the holes are evacuated from the FB. When the FB becomes fully charged with the generated holes, the V_bi,S-FB is reduced to nearly 0 V, becoming effectively flattened. At a critical latch voltage (V_LU), the accumulated holes in the FB are suddenly released toward the S because V_bi,S-FB disappears. These sequential processes were explained and verified by transient simulations with the aid of the Sentaurus TCAD tool (commercial device simulator) in fig. S2. Consequently, the drain current (I_D) abruptly increases, transitioning the 1T-O from a high-resistance state (HRS) to a low-resistance state (LRS). This phenomenon is referred to as a single transistor latch (STL) (28–31).

Figure 2E presents the output characteristics (I_D-V_D) measured at various V_G,1T-O. When V_D is applied to the D, a one-time transition from HRS to LRS via the STL is observed at V_LU. Unlike two-terminal bistable resistors (32, 33), the three-terminal 1T-O modulates V_LU by adjusting V_G,1T-O, which affects V_bi,S-FB. As V_G,1T-O becomes more negative, fewer electrons can overcome V_bi,S-FB, resulting in reduced II and a corresponding decrease in V_LU. In contrast, when input current (I_in) is applied to the D, the 1T-O exhibits repeated STL behavior. Within one cycle of the oscillation, the holes supplied by I_in increase V_bi,D-FB, thereby triggering II near the D, forming a positive feedback loop until STL occurs, and generating an oscillating output voltage (V_out) from the D. The accumulation of holes in the FB corresponds to a charging process, while their sudden effusion represents the discharging process. As long as an I_in of 10 μA is supplied, charging to the FB and discharging from the FB will occur iteratively. Consequently, V_out measured at the D terminal exhibits a triangular waveform oscillating between the top voltage (V_top) and the bottom voltage (V_bot), while the output current (I_out) from the S terminal is characterized by sharp and narrow peaks (34). V_out increases linearly toward V_top due to gradual charging and then abruptly drops to V_bot as a result of rapid discharging by STL, as shown in Fig. 2F. The tunability of f_osc was experimentally confirmed by varying V_G,1T-O, similar to the modulation of V_LU achieved through adjustments to V_G,1T-O, as shown in Fig. 2G. In addition, f_osc was also tuned by modulating both I_in and parallel capacitance (C_par). As shown in fig. S3, f_osc increases with higher I_in and decreases with lower C_par due to the accelerated charging and discharging, in accordance with the relation f_osc = I_in/(C_par·V_pp), where V_pp is defined as V_top − V_bot (30). Changes in the number of interconnected oscillators also affect C_par. This variation in C_par leads to corresponding changes in f_osc, which can be compensated by tuning V_G,1T-O.

To evaluate the variability and reliability of the 1T-O in the proposed CIM, device-to-device (D2D) and cycle-to-cycle (C2C) variations were statistically characterized, as shown in fig. S4. The variations were assessed using the metric of V_LU. Furthermore, forming the S/D of 1T-O by epitaxial growth, rather than by ion implantation, which introduces statistical fluctuations in the junction profile, yields more uniform metallurgical junctions between the n⁺ S/D and the p-type channel and is expected to further improve D2D uniformity.

Characteristics of a 1T-C

To achieve the reconfigurable control of coupling between two 1T-Os, the D and S of 1T-C were connected to the output terminals (drains) of the two 1T-Os, as shown in Fig. 3A. The SEM image of the 1T-C with channel length (L_ch) of 380 nm and width (W_ch) of 180 nm is shown in fig. S5A. The threshold voltage of the 1T-C (V_T,1T-C) was found to be near 0 V, as shown in fig. S5B. To show the suitability of the 1T-C in large-scale CIM, D2D and C2C variations of the 1T-C were also measured, as shown in fig. S6, using V_T,1T-C as a metric. Their low variations can be attributed to the mature CMOS fabrication technology, demonstrating superior reliability and uniformity compared with OIM approaches that rely on non–CMOS-compatible materials and processes.

Fig. 3. Measured characteristics of coupled 1T-Os through 1T-C.

(A) Circuit diagram of two 1T-Os coupled by 1T-C. (B) Oscillating output voltages (V_out,1 from 1T-O1 and V_out,2 from 1T-O2) for various gate voltages of the 1T-C (V_G,1T-C). Out-of-phase synchronization was observed when V_G,1T-C was larger than a criterion value of 3 V. (C) Comparison of measured and simulated phase difference (Δϕ) between the two 1T-Os for various V_G,1T-C. The shaded region indicates various levels for multibit. Five different 1T-O/1T-C combinations were selected for measurement. The top axis shows the calibrated coupling strength (K_ij) derived from the measured Δϕ, illustrating the implementation of the full three-bit weight range in simulation for solving MaxCUT problems.

Then, V_out,1 corresponds to the source voltage of the 1T-C (V_S,1T-C), while V_out,2 corresponds to the V_D of the 1T-C (V_D,1T-C). After the same V_G,1T-O of −2.5 V was applied to each G of the 1T-Os and the same I_in of 10 μA was applied to each D of the 1T-Os, each V_out (V_out,1 and V_out,2) was then measured. The measured V_out,1 and V_out,2 for various V_G,1T-C are compared in Fig. 3B.

The conductance state of the 1T-C channel is determined by voltage differences of the gate-to-source and gate-to-drain (ΔV_GS,1T-C and ΔV_GD,1T-C), which control the coupling strength between 1T-Os by leveraging the charge transfer and adjusting the phase difference (Δϕ). Herein, ΔV_GS,1T-C is defined as V_G,1T-C − V_S,1T-C, and ΔV_GD,1T-C is defined as V_G,1T-C – V_D,1T-C. As shown in fig. S7, ΔV_GS,1T-C on the primary y axis and ΔV_GD,1T-C on the secondary y axis were compared for various values of V_G,1T-C. As V_G,1T-C increases, the Δϕ between 1T-Os tends to become larger up to 180°. For dynamical coupling of two 1T-Os, the condition ΔV_GS,1T-C > V_T or ΔV_GD,1T-C > V_T must be satisfied to induce the on-state in the 1T-C, where the charge transfer between 1T-Os occurs through the 1T-C. Therefore, Δϕ ranging from 0° to 180° is modulated by V_G,1T-C, as shown in Fig. 3C. This experimental observation was also validated through circuit simulations using LTSpice. On the other hand, in spin-based Ising models, a Δϕ of 0° corresponds to parallel spin alignment (e.g., up-up or down-down), resulting in energy minimization through positive coupling. Similarly, a Δϕ of 180° corresponds to antiparallel spin alignment (e.g., up-down or down-up), leading to another energy minimization through negative coupling. In the proposed CIM, a Δϕ of 0° indicates in-phase synchronization, whereas a Δϕ of 180° signifies out-of-phase synchronization. Consequently, the proposed CIM effectively maps spin interactions onto oscillator phase relationships.

Mitigation of frequency variability through gate-biasing

In large-scale CIMs, the number of interconnected oscillators varies with each network configuration. This leads to differences in the equivalent capacitance (C_equiv) due to variations in the connected capacitive loads. This causes variations in f_osc. Specifically, as the C_equiv experienced by each oscillator increases, the f_osc of that oscillator decreases. Consequently, variations in f_osc across oscillators hinder effective coupling, preventing the large-scale CIM from accurately solving COPs.

However, gate-biasing of a 1T-O can mitigate these f_osc variations through mismatch compensation. To investigate this, we mimicked the situation where multiple capacitive loads are connected to the 1T-O by using parallel capacitors that correspond to C_equiv. Figure 4A shows the circuit diagram of the coupled 1T-Os with parallelly connected C_equiv. When 1T-O1 was connected to C_equiv,1 and 1T-O2 was connected to C_equiv,2, V_out,1 and V_out,2 differed from each other. If C_equiv,1 is larger than C_equiv,2, the f_osc of the 1T-O1 is smaller than that of the 1T-O2, leading to unsynchronized V_out,1 and V_out,2. However, by applying a more positive V_G,1T-O1 to the 1T-O1, its f_osc can be increased to match the f_osc level of the 1T-O2. Figure 4B shows the case where a ΔC_equiv (= C_equiv,1 − C_equiv,2) of 100 pF is compensated by the ΔV_G,1T-O (= V_G,1T-O1 − V_G,1T-O2). By applying an appropriate ΔV_G,1T-O, Δϕ between V_out,1 and V_out,2 approaches 180°, indicating clear out-of-phase synchronization. To further verify the compensation effect, we conducted a fast Fourier transform (FFT) analysis to assess whether the two 1T-Os’ f_osc converge to nearly the same value. As shown in the FFT spectra (fig. S8), the coupled 1T-Os exhibit a clear f_osc mismatch before compensation due to ΔC_equiv; after V_G,1T-O control, their f_osc converge to nearly identical values. Furthermore, as shown in Fig. 4C, even with large ΔC_equiv values between the two 1T-Os, applying an appropriate ΔV_G,1T-O minimizes the f_osc mismatch caused by ΔC_equiv. Simulations using LTSpice also replicated this trend. Figure 4D shows the extracted f_osc as a function of the N_osc used in the CIM. Ideally, if f_osc remains consistent regardless of N_osc, effective coupling will be achieved among the 1T-Os in the CIM. However, as N_osc increases, f_osc deviates from the locking range due to the SHIL, which hinders effective coupling. By adjusting the V_G,1T-O biasing, f_osc of the 1T-Os can be tuned, reducing the f_osc variations across 1T-Os and restoring effective coupling. In this way, the proposed CIM can accurately solve COPs by gate-biasing to reduce the mismatch.

Fig. 4. Measured characteristics of coupled 1T-Os with parallelly connected capacitors (C_equiv,1, C_equiv,2) through 1T-C.

(A) Circuit diagram of the coupled 1T-Os parallelly connected to C_equiv through 1T-C to emulate networks in large-scale CIM configurations. (B) Oscillating V_out,1 and V_out,2 for various V_G,1T-O differences (ΔV_G,1T-O = V_G,1T-O2 − V_G,1T-O1) at the fixed C_equiv differences (ΔC_equiv = C_equiv,2 − C_equiv,1). (C) Comparison of measured and simulated ΔV_G,1T-O required to observe out-of-phase synchronization for various ΔC_equiv. (D) Measured and simulated f_osc according to the N_osc. f_osc variation among 1T-Os in a CIM can be compensated by using V_G,1T-O. For actual implementation of this mitigation, additional circuitry that extracts f_osc and transmits the appropriate V_G,1T-O is needed.

While this work demonstrates proof-of-concept compensation, practical large-scale systems will require peripheral circuitry for automated V_G,1T-O control. To address f_osc dispersion among 1T-Os, additional peripheral circuitry for V_G,1T-O control is required. A conceptual diagram of the peripheral system, composed of compact building blocks such as a multiplexer, frequency detector, calibration logic, charge pump, and low-power digital-to-analog converter, is provided in fig. S9. Analogous to phase-locked-loop systems, the architecture adds only modest area and power overhead and remains fully CMOS compatible.

Subharmonic injection locking in the 1T-O

To enhance the robustness and efficiency of synchronization among 1T-Os, SHIL was introduced, as shown in fig. S10. SHIL was implemented by applying a sinusoidal voltage (V_inj) of 2 V with a frequency close to twice the f_osc of the 1T-O through an injection capacitance (C_inj) of 30 pF. The configuration for SHIL is depicted in the inset of fig. S10B. V_out was binarized to phase 1 and phase 2, indicating that the 1T-O was locked to the external signal, as shown in fig. S10A. To clearly distinguish the binarized phases by eliminating other subpeaks, the V_out data were transformed into the frequency domain using an FFT, as shown in fig. S10B. In addition, as shown in fig. S10C, when f_osc was extracted from the measured V_out at various f_inj, a linear relationship with a slope of 1/2 (i.e., f_osc = f_inj/2) was observed within the locking range. Even in the presence of the aforementioned f_osc variations, SHIL can compensate for them as long as they remain within the locking range. However, if each f_osc of the 1T-Os is not within this range, phase binarization cannot be achieved despite the application of SHIL. In such cases, V_G,1T-O can be adjusted to tune f_osc and ensure effective coupling. In short, gate-biasing is the primary method for addressing f_osc variations, with SHIL serving as a secondary approach. It is also important to investigate how V_inj affects SHIL. As shown in fig. S10D, V_inj was varied from 0.5 to 3.0 V. SHIL was not achieved when V_inj was 0.5 V. However, as V_inj increases, phase bifurcation progresses, and the associated statistical variations tend to decrease. These results indicate that the effect of SHIL becomes more pronounced with stronger injection signals (35, 36).

MaxCUT problem solving with the CIM

With the aid of SHIL, which enforces a binary phase and prevents ambiguous phases, the proposed CIM effectively solves MaxCUT problems. The MaxCUT problem is a representative example of COPs, with the objective of partitioning the nodes of a given graph into two complementary sets such that the number of edges between the two sets is maximized (37). As a proof of concept, a simplified MaxCUT problem was solved using CIM hardware. Figure 5 and fig. S11 show various graph configurations with four nodes and different numbers of edges, ranging from three to six. As shown in Figs. 5 (A to E), for a graph with four nodes and four edges, 1T-O1 and 1T-O4 shared the same phase, while 1T-O2 and 1T-O3 shared the other phase, which was out-of-phase relative to 1T-O1. Similarly, as shown in Fig. 5 (F to J), for a graph with four nodes and six edges, 1T-O1 and 1T-O2 shared the same phase, while 1T-O3 and 1T-O4 shared the opposite phase, also out-of-phase relative to 1T-O1. Notably, SHIL was effective not only in a single 1T-O but also in coupled 1T-Os. Across all graph configurations, the 1T-Os were binarized into two distinct phases, corresponding to the ground-state configuration. In contrast, when SHIL was not applied, the CIM failed to solve the problems, as shown in Fig. 5 (B and G) and fig. S12.

Fig. 5. Experimental data after solving the MaxCUT problem with four nodes.

(A) MaxCUT problem with five edges. For all 1T-Cs, V_G,1T-C was set to 4 V. (B) Measured V_out for 1T-Oi (i = 1, 2, 3, and 4) in (A) without SHIL. (C) A close-up view of the shaded region in (B). (D) Measured V_out for 1T-Oi (i = 1, 2, 3, and 4) in (A) with SHIL. (E) A close-up view of the shaded region in (D). (F) MaxCUT problem with six edges. (G) Measured V_out for 1T-Oi (i = 1, 2, 3, and 4) in (F) without SHIL. (H) A close-up view of the shaded region in (G). (I) Measured V_out for 1T-Oi (i = 1, 2, 3, and 4) in (F) with SHIL. (J) A close-up view of the shaded region in (I).

Next, to demonstrate that V_G,1T-O control can also be applied in MaxCUT problem solving, we performed 50 measurement runs on a case where each 1T-O had a different N_osc interconnected, as shown in fig. S13. In a four-node, three-edge graph, two of the 1T-Os were connected to two neighbors, while the remaining two were connected to only one neighbor. Since the number of connections effectively acts as C_equiv for each 1T-O, this configuration induced f_osc dispersion, which often resulted in either no valid cut formation or incorrect solutions, thereby preventing convergence to the correct ground state. However, by applying V_G,1T-O, the slower 1T-Os could be accelerated, allowing the system to converge to the correct solution. Consequently, when comparing the success probability of the CIM (P_suc)—defined as the ratio of the number of trials that successfully identified the true ground-state energy to the total number of trials conducted—a clear enhancement of P_suc was observed.

It is impractical to perform full hardware-based validation for large-scale problems by connecting all 1T-Os and 1T-Cs. Instead, semiempirical simulations were conducted with the aid of MATLAB, based on experimental data from paired 1T-Os and their mediating 1T-C. Using this approach, we conducted semiempirical simulations for a large-scale MaxCUT problem with various numbers of nodes (N_node) and 50% connectivity, using the proposed CIM. Here, as shown in fig. S14, connectivity is defined as the ratio between the number of connected edges and the total number of possible edges. P_suc was extracted to enable comparison between each case. The graphs were generated using the Rudy graph generator (38). The benchmark for the true ground state was established using solutions obtained from the Biq Mac solver, which uses a branch-and-bound algorithm (39). The results in Fig. 6 (A and B) show the Ising energy and the normalized cut-set weight, respectively, for a 100-node MaxCUT problem with 50% connectivity over 50 independent runs. Phase evolution in a single run is shown in fig. S15, offering a visual representation of how the system dynamically seeks the optimal solution over time.

Fig. 6. Simulated data for solving MaxCUT problems with large-scale CIM.

(A) Ising energy versus oscillation cycles. The gray lines represent 50 runs, while the black line highlights a run that successfully finds the solution. a.u., arbitrary units. (B) Normalized cut-set weight versus oscillation cycles. (C) P_suc after solving multi-weight MaxCUT problems for various weights (one-, two-, and three-bit) versus different N_node. (D) P_suc after solving MaxCUT problems with and without V_G,1T-O control.

The effectiveness of the proposed CIM for solving MaxCUT problems stems from its reconfigurable coupling strength, which is enabled by tuning V_G,1T-C, and its ability to minimize frequency dispersion among 1T-Os by controlling V_G,1T-O. This reconfigurability allowed us to implement multiweight MaxCUT problems by assigning discrete coupling strengths between oscillator nodes. On the basis of the experimentally validated ability to achieve up to eight distinct phase states, we extended the simulation framework to support weighted graphs with one-, two-, and three-bit weights. Simulations were conducted across various graph sizes with 50% connectivity. As shown in Fig. 6C, the P_suc increases with higher bit-width weights. The improvement arises because additional discrete coupling levels provide greater flexibility to compensate for D2D variability and connectivity imbalance. In one-bit coupling, all interactions are fixed to a single strength, which can be insufficient when oscillator frequencies are dispersed. In contrast, two- and three-bit coupling attenuate connections, reduce imperfections, and promote more reliable convergence to the ground state. This demonstrates not only the versatility of the proposed CIM for solving multiweight MaxCUT problems but also its robustness under practical nonideal conditions, highlighting the potential for scalable and reconfigurable Ising computation.

We further demonstrated that reducing frequency dispersion among oscillators significantly enhances P_suc. When the f_osc variation among the 1T-Os was large, P_suc was low even with injection locking because of the excessive capacitive load on each oscillator. However, by properly adjusting V_G,1T-O to reduce f_osc variation, P_suc was significantly improved compared to the uncompensated case, as shown in Fig. 6D. Furthermore, as shown in fig. S16, thanks to the inherent parallelism of the CIM, the time to solution was significantly shorter than that of conventional CPU-based algorithms solving the same problem. This advantage became more pronounced as the problem size increased and the complexity grew.

DISCUSSION

In this work, we have demonstrated a highly scalable CIM using 100% silicon MOSFETs (Si-MOSFETs). The CIM consists of 1T-Os and 1T-Cs, which correspond to spin states and their interaction. By using a single Si-MOSFET as both a frequency-tunable 1T-O and a reconfigurable 1T-C, we significantly reduce the hardware complexity of conventional OIMs, thereby achieving superior scalability and integration density compared to circuit-based oscillators and resistor- or capacitor-based couplers. The frequency tunability provides an effective way of mitigating f_osc variations caused by different capacitive loads in large-scale CIM implementations. In addition, the precise reconfigurability of the coupling strength using 1T-C enables flexible connectivity for solving diverse COPs. Distinctive advantages of this work compared to previous reports are illustrated in fig. S17 and compared in table S1. This work demonstrates a CIM using Si-MOSFETs as oscillators rather than circuits and as couplers instead of capacitors and resistors that are not easily scalable, thereby mitigating variations in f_osc to effectively solve COPs. To validate our proposed CIM, we applied it to solving MaxCUT problems. Experimental results demonstrated that the system successfully identified optimal spin configurations, proving the feasibility of our approach. This work establishes a ground-breaking framework for efficient and scalable CIM, offering a viable alternative to conventional von Neumann–based heuristic solvers.

MATERIALS AND METHODS

Device fabrication

The fabrication of the 1T-O starts with a three-step ion implantation on a (100) bulk-Si wafer. The top source region was formed via shallow implantation of high-dose arsenic (As), the FB region was implanted with a moderate dose of boron (B) at a medium depth, and the bottom drain was created through deep implantation of high-dose phosphorus (P). An annealing process was then conducted to activate the dopants. Next, the vertical pillar was defined using photolithography and plasma etching. The deposition of the first interlayer dielectric (ILD) was followed to electrically isolate each 1T-O. Then, gate dielectrics and n⁺ in situ–doped poly-crystalline silicon (poly-Si) gate were sequentially deposited, fully wrapping the vertical pillar due to their conformal nature. Afterward, the gate was patterned using another photolithography step and plasma etching. The second ILD was deposited to isolate all electrodes from the overlying metal lines. Metallization using Ti/TiN/W layers was then performed to form electrical contacts and interconnects.

On the other hand, not all components comprising the CIM need to be integrated simultaneously. Some elements can be monolithically integrated using a stacked “one-over-the-other” configuration without significantly compromising the aforementioned advantages in scalability and manufacturing efficiency. For example, 1T-Cs can be positioned above the vertical 1T-Os to minimize the overall footprint, as shown in fig. S18, although this concept could not be demonstrated in the present work because of limitations in the fabrication facilities. For the STL at low V_LU, a single-crystalline silicon channel is preferred for a vertical 1T-O, whereas for monolithic integration, a poly-Si channel is preferred for a horizontal 1T-C, which is a type of thin-film transistor.

Characterization and measurement

The dc electrical characterization of the 1T-O and 1T-C was conducted using a semiconductor parameter analyzer (B1500A, Keysight). To apply sinusoidal injection signal to the 1T-O for SHIL, a function generator (AFG 3022B, Tektronix) was used. The V_out of the 1T-O alone and the coupled 1T-Os were measured using an oscilloscope (TBS 200B, Tektronix). The experimental setup for the proposed CIM is shown in fig. S19.

Simulations

Device simulations were performed using the Sentaurus TCAD simulator (Synopsys) to analyze the STL. All device parameters were set to values closely matching those obtained from TEM images. The 1T-O was modeled as a voltage-controlled threshold switch in parallel with a capacitor for semiempirical simulations of large-scale arrays in the CIM using SPICE software (LTspice, Analog Devices). To address the MaxCUT problems through multiple simulation runs, we used a stochastic differential equation solver within a MATLAB simulation framework to closely replicate the dynamics of the coupled Si oscillating transistor system under injection locking. The fitting of the coupling strength, injection locking strength, and frequency dispersion were based on the experimental observations.

Supplementary Materials

This PDF file includes:

Figs. S1 to S19

Table S1

Supplementary Text