Fig. 4. Gate-tunable synaptic memory and working mechanism.

a Normalized transient photoresponse and decay curves under varying V_gs (from −4 to 0 V). b Distinct memory states: long-term memory (top, V_gs = 0 V) and short-term memory (bottom, V_gs = −4 V), where t_re denotes the retention time. c Benchmark of dynamic memory range and retention tunability ratio, comparing this work (red star) with reported high-temperature optoelectronic synaptic devices (OSDs). d Band diagrams illustrating the mechanism of gate-modulated charge trapping/detrapping dynamics under high V_gs (top) and low V_gs (bottom), where E_C, E_F and E_V represent the conduction band minimum, Fermi level, and valence band maximum, respectively; the blue circles with ‘-‘ and red circles with ‘+‘ represent electrons and holes; and the arrows indicate carrier trapping and detrapping processes. e Transfer curves of MoS₂ OSD with SiO₂ dielectric measured in dark, illuminated, and post-illumination state at room temperature (V_ds = 0.5 V). Inset: photoresponse at V_gs = −12 V and V_gs = −2 V. f Schematic illustrating the operating principle of the device with SiO₂ dielectric. The blue circles with ‘-‘ and red circles with ‘+‘ represent electrons and holes; and the red arrows indicate carrier trapping processes. g Transfer curves of MoS₂ OSD with Pt electrode measured in dark, illuminated, and post-illumination state at room temperature (V_ds = 0.5 V). Inset: photoresponse at V_gs = -3.5 V and V_gs = -0.5 V. h Schematic view of the mechanism of the device with Pt electrode. The blue circles with ‘-‘ and red circles with ‘+‘ represent electrons and holes; and the red arrows indicate carrier transport processes.