Figure 5. A Minimal Model for Dual-Task Response Times: Incorporating Task Switching Costs into Sequential Processing Models.

(A) Minimal model capable of accounting for the critical observations in our interference paradigm (see Results and Discussion for a more detailed description). Each task consists of three basic processing stages: perceptual (P), central (C), and motor (M) processes. It is assumed that only the central process establishes a bottleneck whereas other stages can be carried out in parallel with stages of another concurrent task [ 8, 24]. Central processes, which are assumed to rely on stochastic evidence accumulation mechanisms and therefore make a major contribution to response-time variability [ 27], are depicted with triangles. Non-decision processes, which have a relatively fixed duration, are depicted with boxes. The model supposes that a first central decision is required to select which task to perform first. We refer to this stage as task setting. We assume that its duration is longer at short SOAs, when both stimuli are in competition, than at long SOAs, when a single stimulus is presented. A second postulate is that there is a temporary inhibition of the response to the second task, implying that it cannot be executed until the first task has been disengaged, as observed in task-switching paradigms [ 14]. We refer to this stage as task disengagement. Note how, during the interference regime, all three central decisional processes (triangles) follow each other in time, indicating saturation of the central system, which causes the observed response delays (dashed lines). Those delays essentially vanish as SOA increases.

(B) Pattern of results predicted by the model (same format as in Figure 2B). All the key observations can be fitted with a single set of parameters. The stage durations, in milliseconds, are: P(Number) = 350, P(Tone) = 320, C(Number) = 530, C(Tone) = 580, M(Number) = 50, M(Tone) = 30, Task Disengagement = 600, and Max Task Setting = 200. The fit yields a mean square error (averaged across all conditions) of 42 ms.