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. 2008 Aug 29;4(8):e1000159. doi: 10.1371/journal.pcbi.1000159

Figure 11. Comparing the hierarchical model [3] with the networks generated by our method, with regard to latency.

Figure 11

On the x-axis is the level in the hierarchy an area is in when only considering the shortest possible route from the source node. On the y-axis is the first spike latency in ms. In part A and D the level structure of the hierarchical model can be seen, in part B and D the same is plotted for the structure suggested by our results. Area names (indicated as in Figure 9) are included for general reference, overlapping labels omitted for clarity. Areas in a higher level in a hierarchy should have longer latencies then areas lower in the hierarchy.