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The number of metal layers increases with chip area as predicted by equation (3.3). The y-axis represents the number of layers containing wire (the number of metal layers plus the silicon layer) multiplied by the process size, and the x-axis represents chip area. The scaling exponent is 0.53 (OLS) and r2 is 0.57. Data are from (C. Ludloff 2007, http://sandpile.org/).
