Table 1.
Different states for each element (here NAND gates) for the circuit shown in figure 2a.
| input | G1 | G2 | G3 | G4 | G5 | output |
|---|---|---|---|---|---|---|
| 00 | 1 | 1 | 1 | 1 | 1 | 11 |
| 01 | 1 | 0 | 0 | 1 | 1 | 11 |
| 10 | 1 | 1 | 1 | 0 | 1 | 01 |
| 11 | 0 | 1 | 1 | 0 | 0 | 00 |
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