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. 2009 Jul 9;3:21. doi: 10.3389/neuro.11.021.2009

Figure 1.

Figure 1

(A) Processor with a single core featuring Level 1 instruction and data caches (L1| and L1D), Level 2 cache (L2), and main memory (RAM) accessed via the Front Side Bus (FSB); the core is equipped with subunits for e. g. vector arithmetics, floating point processing, memory management and an interrupt controller. (B) A multi-core processor with four cores where two cores share a L2 cache, respectively. (C) A multi-core processor where all cores have a private L2 cache but a L3 cache shared between all four cores.