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. Author manuscript; available in PMC: 2010 Apr 1.
Published in final edited form as: IEEE Trans Neural Syst Rehabil Eng. 2009 Apr;17(2):176ā€“182. doi: 10.1109/TNSRE.2008.2009307

Fig 2.

Fig 2

Decoder and control signal of the dual-supply design. a) Decoder circuit b) Control signal and its timing for configuring the counter: First, the reset pulse is generated by temporarily turning off Vāˆ’. Then, the clock signal, embedded in V+, is applied. Once an active channel of the multiplexer is configured, the stimulating current can be passed from the shared contact through the active channel in the electrode to GND.