Skip to main content
. Author manuscript; available in PMC: 2010 Apr 1.
Published in final edited form as: IEEE Trans Neural Syst Rehabil Eng. 2009 Apr;17(2):176–182. doi: 10.1109/TNSRE.2008.2009307

Fig 3.

Fig 3

Decoder and control signal of the single-supply design. a) Decoder circuit b) The control signal and its timing to configure the counter. The reset is initiated by a 2xV+ pulse applied to the V+ line. The clock signal is then followed to configure the counter and multiplexers.