Figure 4.

Illustrations relating the physical structure of the prototype active pixels to their circuit diagrams, with color coding to indicate the correspondence between parts of the circuit and their physical implementation in the pixel. Three-dimensional drawings of the detailed structure of (a) PSI-2 and (c) PSI-3 pixels. Each drawing illustrates four adjoining pixels and reveals varying degree of detail. Note that dimensions in the direction perpendicular to the substrate have been exaggerated for clarity of presentation. Schematic circuit diagrams for prototype arrays (b) PSI-2 and (d) PSI-3. For each diagram, the dashed line delineates an individual pixel from other elements on the array. Each pixel design incorporates: a photodiode structure, PD, with capacitance per pixel of C_PD (in blue); a dual-gate addressing transistor TFT_ADDR and a source-follower transistor, TFT_SF, providing an amplification stage (both shown in light green); a reset transistor, TFT_RST, and its control lines (in yellow); and a readout transistor, TFT_RO, located on the periphery of the array and used to allow integration of the amplified signal on the data line capacitance, C_data, prior to sampling by an external preamplifier. For PSI-3, additional circuit elements include: a common-source amplifier transistor, TFT_CSA, and an active load transistor, TFT_AL, which together provide the first of two stages of amplification (in purple); a feedback capacitor, C_FB, (in orange), which serves as the pixel storage capacitor; and a ground line (in dark gray). V_bias represents the reverse bias voltage externally applied to the photodiode. V_D-RST and V_G-RST refer to the voltage applied to the drain electrode and gate electrode of TFT_RST in the PSI-2 and PSI-3 designs, respectively. Finally note that, for PSI-3, adjacent pixels share common lines which provide supply voltages (i.e., V_CC, V_G-AL, and V_GND along the data line direction and V_G-RST along the gate line direction). Values for these voltages are given in Table 2.