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. Author manuscript; available in PMC: 2010 Dec 1.
Published in final edited form as: Nano Lett. 2009 Dec;9(12):4539–4543. doi: 10.1021/nl903030h

Figure 3.

Figure 3

(A) SEM image of a porous silicon nanowire device. The inset shows a higher resolution SEM image highlighting the porous structure. The scale bar in inset is 100 nm. (B) Drain current (Id) versus drain voltage (Vd) at variable gate voltages.