Skip to main content
. 2009 Dec 1;3(4):044111. doi: 10.1063/1.3270523

Figure 3.

Figure 3

(a) The multilevel fabrication method; (b) a scanning electron microscope image (in tilted view) of the resulting Si master template; (c) optical micrograph of the structured PDMS replica, with the grating structures shown; (d) a monolithic PDMS chip after the final assembly.