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. Author manuscript; available in PMC: 2010 Aug 6.
Published in final edited form as: Lab Chip. 2009 Aug 20;9(21):3131–3143. doi: 10.1039/b904354c

Figure 5.

Figure 5

Electrical representations and CAD designs of (a) a NAND gate, (b) a buffer, and (c) an XOR gate. Inter-layer connections in individual violet squares have an internal hole between the ‘control’ and ‘flow’ layers.