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. Author manuscript; available in PMC: 2010 Aug 27.
Published in final edited form as: Chem Soc Rev. 2010 Jan 4;39(3):912–922. doi: 10.1039/b822556g

Figure 6.

Figure 6

(a) Schematic diagram of fabricating vertical nanochannels:14 (i) photolithography defines pattern structures; (ii) vertical trenches with smooth sidewalls are etched by either DRIE or anisotropic wet etching (KOH); (iii) thermal oxide growth further decreases the gap size; (iv) uniform PECVD oxide is deposited to seal narrow trenches; (v) backside etching of the Si wafer yields thin membranes over a wide area (~6 inch wafers). (b) Cross-sectional SEM micrographs of slot-like vertical nanochannels with a uniform gap size of 72 nm and 55 nm. The channels are etched by KOH etching and have a depth of 28 μm. The channels are completely sealed by depositing 3 μm thick PECVD oxide.