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. Author manuscript; available in PMC: 2010 Aug 31.
Published in final edited form as: J Neural Eng. 2009 Mar 13;6(2):026005. doi: 10.1088/1741-2560/6/2/026005

Figure 1.

Figure 1

Cross-sectional view of wafer level fabrication. (a) Parylene deposited on SiO2 sacrificial layer and the SU-8 patterned shank. (b) Parylene encapsulated SU-8 structure. (c) 9260 resist patterned to form thick mask over shank. (d) Etched and released final structure. Photolithography masks used steps in (a, c).