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. Author manuscript; available in PMC: 2011 Oct 15.
Published in final edited form as: J Neurosci Methods. 2010 Jul 15;192(2):187–192. doi: 10.1016/j.jneumeth.2010.06.030

Figure 3.

Figure 3

The patch-clamp system was implemented using silicon-on-sapphire (SOS) technology. The insulating substrate in SOS (top) reduces parasitic capacitance and allows fabrication of large resistors to implement Rf with no degradation in frequency response. The insulating substrate reduces crosstalk between channels and allows devices to operate at faster speeds than conventional bulk CMOS technology (bottom).