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. 2010 Aug 23;1(2):658–675. doi: 10.1364/BOE.1.000658

Fig. 3.

Fig. 3.

Parallelization scheme of the GPU-accelerated MCML code. Note that the number of thread blocks Q is matched to the number of SMs available and the number of threads P in each block is a many-to-one mapping (in this case, Q=15 and P=896 for GTX 480).