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. 2010 Aug 23;1(2):658–675. doi: 10.1364/BOE.1.000658

Fig. 4.

Fig. 4.

The simulation time dependance on the shared memory size used for caching of the high-fluence region of the A[r][z] array. The speedup is compared to the CPU-MCML execution time of 14418 s or ~4 h.