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. Author manuscript; available in PMC: 2011 Jan 11.
Published in final edited form as: Dig Tech Papers. 2009 Jun 21;2009:1626–1629. doi: 10.1109/SENSOR.2009.5285771

Figure 4.

Figure 4

Left die photo shows CMOS as returned from foundry. Boxes indicate layout of underlying CMOS architecture. Right die photo shows chip after fabrication of FBAR structures, including the passive test structure along the top edge.